From: "Michael H. Nguyen" <michael.h.nguyen@xxxxxxxxx> This is v5 of the series sent here: http://lists.freedesktop.org/archives/intel-gfx/2014-November/055141.html This version incorporates the following feedback from v4. - 0/7 Move 'pending_read_domains |= I915_GEM_DOMAIN_COMMAND' after the parser (danvet) - 1/7 Move purged check inside the loop (danvet) - 6/7 Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get fnc (danvet) - 7/7 Move pin/unpin calls inside i915_parse_cmds() (Chris W) Issue: VIZ-4719 Brad Volkin (7): drm/i915: Implement a framework for batch buffer pools drm/i915: Use batch pools with the command parser drm/i915: Add a batch pool debugfs file drm/i915: Add batch pool details to i915_gem_objects debugfs drm/i915: Use batch length instead of object size in command parser drm/i915: Mark shadow batch buffers as purgeable drm/i915: Tidy up execbuffer command parsing code Documentation/DocBook/drm.tmpl | 5 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_cmd_parser.c | 99 ++++++++++++++++--- drivers/gpu/drm/i915/i915_debugfs.c | 86 ++++++++++++++-- drivers/gpu/drm/i915/i915_dma.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 24 +++++ drivers/gpu/drm/i915/i915_gem.c | 3 + drivers/gpu/drm/i915/i915_gem_batch_pool.c | 154 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 99 +++++++++++++++---- 9 files changed, 430 insertions(+), 42 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.c -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
