On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> From: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
>
> As per latest pm guide, we need to do this also on
> past hsw.
Yep, matches the doc.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
see such a thing documented in the HSW PM guide I have here. Maybe we can
just drop the HSW special case?
Also I wonder if we want this on CHV too. I should probably know, but I
dont't. I'll go bash some registers and see what they say...
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 6a0c3fb..86a755a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -120,8 +120,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
> DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
>
> /* WaRsForcewakeWaitTC0:ivb,hsw */
> - if (INTEL_INFO(dev_priv->dev)->gen < 8)
> - __gen6_gt_wait_for_thread_c0(dev_priv);
> + __gen6_gt_wait_for_thread_c0(dev_priv);
> }
>
> static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> --
> 1.9.3
--
Ville Syrjälä
Intel OTC
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