On Tue, Nov 11, 2014 at 02:16:32PM +0200, Ville Syrjälä wrote: > On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote: > > On Tue, Nov 11, 2014 at 10:22:11AM +0000, Chris Wilson wrote: > > > On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote: > > > > On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote: > > > > > On Tue, Nov 04, 2014 at 04:51:38AM -0800, Rodrigo Vivi wrote: > > > > > > Patch drm/i915: Make the physical object coherent with GTT - Reviewer: > > > > > > > > > > Already has my r-b. > > > > > > > > I still would like to see a little testcase here, e.g. a new mode to > > > > kms_cursor_crc which uses gtt mmap uploads instead of pwrite. > > > > > > But that doesn't block this patch, as the kernel already exposes and > > > userspace already uses gtt mmap updates to the cursor. The patch just > > > removes the barrier to do so using early chipsets as well. > > > > Well yeah, but that existing code has piles of tests already to make sure > > that gtt writes are somewhat coherent with pwrite, and another test that > > pwrite is coherent with the actual cursor scanned out by hw. > > Actually pwrite isn't coherent with scanout currently on LLC platforms > if you do the pwrite when the bo already has cache_level==NONE but it's > not yet pinned to the display. So seems our pwrite tests aren't entirely > comprehensive currently if they don't hit this. I still haven't seen > the fabled patch from Chris that would fix this. This patch includes an unconditional clflush for phys writes (or at least this patch should be that patch) which is what I thought we were arguing about at the time. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
