On Fri, Nov 07, 2014 at 07:34:31AM -0800, Neil Roberts wrote: > The predicate source registers are needed to implement conditional > rendering without stalling. The two source registers are used to load > the previous values of the PS_DEPTH_COUNT register saved from > PIPE_CONTROL commands. These can then be compared and used to set the > predicate enable bit via the MI_PREDICATE command. > > Signed-off-by: Neil Roberts <neil@xxxxxxxxxxxxxxx> Reviewed-by: Brad Volkin <bradley.d.volkin@xxxxxxxxx> > --- > > There is a corresponding patch for Mesa which is using these registers > on the mailing list here: > > http://lists.freedesktop.org/archives/mesa-dev/2014-November/070347.html > > There are some other registers such as MI_PREDICATE_DATA which can be > used for more advanced predicate checking but I haven't added them to > the list because they aren't needed to implement > GL_NV_conditional_render. > > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 4c35e2a..9732155 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -408,6 +408,8 @@ static const u32 gen7_render_regs[] = { > REG64(PS_INVOCATION_COUNT), > REG64(PS_DEPTH_COUNT), > OACONTROL, /* Only allowed for LRI and SRM. See below. */ > + REG64(MI_PREDICATE_SRC0), > + REG64(MI_PREDICATE_SRC1), > GEN7_3DPRIM_END_OFFSET, > GEN7_3DPRIM_START_VERTEX, > GEN7_3DPRIM_VERTEX_COUNT, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ea84e1e..9275d41 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -314,6 +314,8 @@ > #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ > #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) > > +#define MI_PREDICATE_SRC0 (0x2400) > +#define MI_PREDICATE_SRC1 (0x2408) > > #define MI_PREDICATE_RESULT_2 (0x2214) > #define LOWER_SLICE_ENABLED (1<<0) > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
