On Tue, Oct 28, 2014 at 11:45:35AM -0700, Rodrigo Vivi wrote: > VLV PSR support PSR per pipe, including the status. So we have to check > if it is enabled per pipe on status. > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 82e47da..774eb6c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2076,7 +2076,26 @@ static bool is_edp_psr(struct intel_dp *intel_dp) > return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; > } > > -static bool intel_edp_is_psr_enabled(struct drm_device *dev) > +/** > + * vlv_edp_is_psr_enabled_on_pipe > + * @dev: DRM device > + * @pipe: pipe to check for PSR status. > + * > + * VLV PSR implements PSR per pipe. This function allows to check if it is > + * enabled on given pipe. > + */ > +static bool vlv_edp_is_psr_enabled_on_pipe(struct drm_device *dev, int pipe) Adding functions without users makes imo patch review harder. > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + uint32_t val; > + > + val = I915_READ(VLV_PSRSTAT(pipe)) & > + VLV_EDP_PSR_CURR_STATE_MASK; > + return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || > + (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); > +} > + > +static bool hsw_edp_is_psr_enabled(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > @@ -5066,7 +5085,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > * hard to tell without seeing the user of this function of this code. > * Check locking and ordering once that lands. > */ > - if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { > + if (IS_HASWELL(dev) && hsw_edp_is_psr_enabled(dev)) { Or is there something missing here? Otherwise this hunk here looks like a separate patch ... -Daniel > DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); > return; > } > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx