>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Rodrigo Vivi >Sent: Wednesday, October 29, 2014 12:16 AM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Cc: Vivi, Rodrigo >Subject: [PATCH 08/10] drm/i915: VLV/CHV PSR debugfs. > >Add debugfs support for Valleyview and Cherryview considering that >we have PSR per pipe and we don't have any kind of >performance counter as we have on other platforms that support PSR. > >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >--- > drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++++++++++++++++++++++++++----- > 1 file changed, 29 insertions(+), 5 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c >index a79f83c..3edc20f 100644 >--- a/drivers/gpu/drm/i915/i915_debugfs.c >+++ b/drivers/gpu/drm/i915/i915_debugfs.c >@@ -2126,6 +2126,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > struct drm_device *dev = node->minor->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > u32 psrperf = 0; >+ u32 stat[3]; >+ enum pipe pipe; > bool enabled = false; > > intel_runtime_pm_get(dev_priv); >@@ -2140,14 +2142,36 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > seq_printf(m, "Re-enable work scheduled: %s\n", > yesno(work_busy(&dev_priv->psr.work.work))); > >- enabled = HAS_PSR(dev) && >- I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; >- seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled)); >+ if (HAS_PSR(dev)) { >+ if (HAS_DDI(dev)) >+ enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; >+ else { >+ for_each_pipe(dev_priv, pipe) { >+ stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & >+ VLV_EDP_PSR_CURR_STATE_MASK; >+ if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || >+ (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) I think it is better to include 'state 2' (transition to active) also here. We almost always go to state3 from state 2, before exiting (to state 5) Unless it is an 'abort' case. >+ enabled = true; >+ } >+ } >+ } >+ seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); > >- if (HAS_PSR(dev)) >+ if (!HAS_DDI(dev)) >+ for_each_pipe(dev_priv, pipe) { >+ if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || >+ (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) >+ seq_printf(m, " pipe %c", pipe_name(pipe)); >+ } >+ seq_puts(m, "\n"); >+ >+ /* CHV PSR has no kind of performance counter */ >+ if (HAS_PSR(dev) && HAS_DDI(dev)) { > psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & > EDP_PSR_PERF_CNT_MASK; >- seq_printf(m, "Performance_Counter: %u\n", psrperf); >+ >+ seq_printf(m, "Performance_Counter: %u\n", psrperf); >+ } > mutex_unlock(&dev_priv->psr.lock); > > intel_runtime_pm_put(dev_priv); >-- >1.9.3 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
