Hi Rodrigo, >-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of >Rodrigo Vivi >Sent: Wednesday, October 29, 2014 12:16 AM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Cc: Vivi, Rodrigo >Subject: [PATCH 01/10] drm/i915: Add PSR registers for PSR VLV/CHV. > >Baytrail (Valleyview) and Braswell (Cherryview) uses a complete different >implementation of PSR that we currently have supported for >Haswell and Broadwell. So let's start by adding registers definitions. > >I usually don't like commit that adds just registers without using, >but after I put all in one commit I realized that no one would want >to take the AR to review it so I decided to split in order to make >reviewer's life easier. Only last commit in this series will actually >enable the PSR on intel enable panel path. > >But as it happens currently with HSW/BDW the plan is to let it >disabled by default (protected by kernel parameter) >while we are able to fully validate it. > >Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >--- > drivers/gpu/drm/i915/i915_reg.h | 37 >+++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index 77fce96..771780a 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -2509,6 +2509,43 @@ enum punit_power_well { > #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) > #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) > >+/* VLV eDP PSR registers */ >+#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) >+#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) >+#define VLV_EDP_PSR_ENABLE (1<<0) >+#define VLV_EDP_PSR_RESET (1<<1) >+#define VLV_EDP_PSR_MODE_MASK (7<<2) >+#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) >+#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) >+#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) >+#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) >+#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) >+#define VLV_EDP_PSR_DBL_FRAME (1<<10) >+#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) >+#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 >+#define VLV_EDP_PSR_INT_TRANSITION (1<<24) Bit 24 is Reserved for CHV. The PSR interrupt bits for CHV are moved to pipe control registers. [Looks like we do not use this bit anywhere in our code] >+#define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB) >+ >+#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) >+#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) >+#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) >+#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) >+#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) >+#define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB) >+ >+#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) >+#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) >+#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) >+#define VLV_EDP_PSR_CURR_STATE_MASK 7 >+#define VLV_EDP_PSR_DISABLED (0<<0) >+#define VLV_EDP_PSR_INACTIVE (1<<0) >+#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) >+#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) >+#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) >+#define VLV_EDP_PSR_EXIT (5<<0) >+#define VLV_EDP_PSR_IN_TRANS (1<<7) >+#define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB) >+ > /* HSW+ eDP PSR registers */ > #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) > #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) >-- >1.9.3 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
