Re: i915.fastboot bug report - not working on coreboot

[Charles Devereaux <intelgfx@xxxxxxxxxxx>]

Hello

(IIRC, there is no VBT  or INT 10H support yet in coreboot native video init)

Regarding EDID, it's handled from intel_gma_init in coreboot/src/northbridge/intel/i945/gma.c.
The only thing I see that could be linked to a preferred mode is in decode_edid from coreboot/src/lib/edid.c :
                if (edid[0x18] & 0x02) {
                        printk(BIOS_SPEW, "First detailed timing is preferred timing\n");
                        has_preferred_timing = 1;
                }
(...)
                /* detailed timings */
                printk(BIOS_SPEW, "Detailed timings\n");
                has_valid_detailed_blocks = detailed_block(out, edid + 0x36, 0);
                if (has_preferred_timing && !did_detailed_timing)
                        has_preferred_timing = 0; /* not really accurate... */

Maybe disabling has_preferred_timing  if there are no did_detailed_timing is wrong?

I'm sorry but my understanding of coreboot video initialization is too limited.  Gluglug, could you suggest someone that could help on that issue? Addressing it will enable i915.fastboot support.

Jesse, if meanwhile you can send me fastboot patch to handle that, I will be happy to test it and report the result.

(At the moment, even if i915.fastboot fails as reported above, I get some blinking in Xorg, which is resolved after going back and forth to a text console)

Thanks
Charles

On Thu, Oct 30, 2014 at 5:34 PM, Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote:

On Thu, 23 Oct 2014 16:44:26 -0400
Charles Devereaux <intelgfx@xxxxxxxxxxx> wrote:

> [    0.529733] [drm:intel_set_config_compute_mode_changes], modes are
> different, full mode set
> [    0.529736] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 54167
> 1024 1048 1184 1344 768 771 777 806 0x0 0xa
> [    0.529740] [drm:drm_mode_debug_printmodeline], Modeline 11:"1024x768"
> 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa

This looks like the issue.  The BIOS programs a slightly different
1024x768 mode than what the kernel tries to apply.  Looks like reduced
vs non-reduced blanking approximately.

We could adjust the fastboot code to handle that, or change coreboot to
use the preferred mode from the EDID of the display or make the VBT
match, which is presumably what the kernel is using.

--
Jesse Barnes, Intel Open Source Technology Center

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