On 10/23/2014 09:50 PM, Jesse Barnes wrote:
This is useful for checking things later. Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_drv.h | 4 +++ drivers/gpu/drm/i915/intel_hdmi.c | 61 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+)
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diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 8b5f3aa..75efe4c 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c
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@@ -320,6 +362,17 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, POSTING_READ(ctl_reg); } +static bool hsw_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 val = I915_READ(ctl_reg); + + return val & VIDEO_DIP_ENABLE;
Haswell docs list bit 31 of VIDEO_DIP_CTL as reserved. Looking at hsw_set_infoframe(), it seems that you would have to test for the enable bits for the different infoframe types instead.
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