On Wed, Oct 15, 2014 at 06:34:41PM +0100, Damien Lespiau wrote: > Ville found that the sequencing I had to re-program the DDB wasn't quite > correct and so this is an attempt to do better. > > This series reworks patch: > > [PATCH 78/89] drm/i915/skl: Flush the WM configuration > > of the initial SKL Stage 1 series. The core of the issue is now documented in a > comment, so I won't repeat it here again. > > -- > Damien > > Damien Lespiau (3): > drm/i915/skl: Stage the pipe DDB allocation > drm/i915/skl: Flush the WM configuration Replied to this with r-b and some comments. > drm/i915/skl: Log the order in which we flush the pipes in the WM code And the other two look good too, so for the entire series: Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 152 ++++++++++++++++++++++++++++++++++++++-- > 2 files changed, 146 insertions(+), 7 deletions(-) > > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
