On Thu, Sep 04, 2014 at 12:27:12PM +0100, Damien Lespiau wrote:
> We now need to allocate space in the DDB for planes being scanned out
> ourselves. The data structure to represent an allocation mirrors what
> we'll need to write in the registers later on: (start, end).
>
> We add that allocation datat to the skl_wm_values structure as part of
> the values to program the hardware with.
>
> v2: Split planes and cursor for consistency.
>
> v3: Make the skl_ddb_entry_size() parameter const
>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
Yeah I'm mostly happy with the fixup patch for the inclusive vs.
exclusive, so
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3764ad5..de278a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1381,8 +1381,27 @@ struct ilk_wm_values {
> enum intel_ddb_partitioning partitioning;
> };
>
> +struct skl_ddb_entry {
> + uint16_t start, end; /* in number of blocks */
> +};
> +
> +static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
> +{
> + /* end not set, clearly no allocation here. start can be 0 though */
> + if (entry->end == 0)
> + return 0;
> +
> + return entry->end - entry->start + 1;
> +}
> +
> +struct skl_ddb_allocation {
> + struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
> + struct skl_ddb_entry cursor[I915_MAX_PIPES];
> +};
> +
> struct skl_wm_values {
> bool dirty[I915_MAX_PIPES];
> + struct skl_ddb_allocation ddb;
> uint32_t wm_linetime[I915_MAX_PIPES];
> uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
> uint32_t cursor[I915_MAX_PIPES][8];
> --
> 1.8.3.1
>
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--
Ville Syrjälä
Intel OTC
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