On Tue, Oct 28, 2014 at 10:57:38AM -0700, Jesse Barnes wrote: > On Thu, 16 Oct 2014 20:52:33 +0300 > ville.syrjala@xxxxxxxxxxxxxxx wrote: > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > In case the cmnlane power well is down but cmnreset isn't asserted we > > would currently skip the off+on toggle for the power well. That could > > leave cmnreset deasserted while cmnlane is powered down which might > > lead to problems with the PHY. > > > > To avoid such issues skip the cmnlane toggle only if both cmnlane and > > disp2d wells are up and cmnreset is already deasserted. In all other > > cases power down the cmnlane well which will also make sure cmnreset > > gets asserted correctly while cmnlane is powered down. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++----- > > 1 file changed, 2 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > > b/drivers/gpu/drm/i915/intel_runtime_pm.c index 36749b9..f6b4e8d > > 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -1137,12 +1137,9 @@ static void vlv_cmnlane_wa(struct > > drm_i915_private *dev_priv) struct i915_power_well *disp2d = > > lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); > > > > - /* nothing to do if common lane is already off */ > > - if (!cmn->ops->is_enabled(dev_priv, cmn)) > > - return; > > - > > /* If the display might be already active skip this */ > > - if (disp2d->ops->is_enabled(dev_priv, disp2d) && > > + if (cmn->ops->is_enabled(dev_priv, cmn) && > > + disp2d->ops->is_enabled(dev_priv, disp2d) && > > I915_READ(DPIO_CTL) & DPIO_CMNRST) > > return; > > > > > Yeah looks ok. Do we have any bugs we know this fixes? Not sure. I don't really know if I ever saw a machine that really needed this toggling. But I did simulate crappy BIOS for it once by turning on the cmn well but leaving everything else off, and after the toggle w/a nothing got stuck so it seemed to do the right thing at least :) > I'm hoping the > remaining VLV DP training failures are fixed either by something like > this or your panel power sequencer fixes. Me too. I think it should be pretty solid after those. Then we just need to figure out how to make it fast again if it really got much slower. But at least the massive init time increase might be fixed by the timestamp init patch I posted today. > > Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
