On Wed, Oct 22, 2014 at 10:09:49AM +0100, Arun Siluvery wrote: > The number of DWords should be even when doing ring emits as > command sequences require QWord alignment. It looks like we could just pad at the end of the batch instead of one NOP per register write? Also, It looks like we could use the LRI variant that can write more than one register in one go (separate patch)?. -- Damien > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 12a546f..79211ae 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -680,7 +680,7 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring) > if (ret) > return ret; > > - ret = intel_ring_begin(ring, w->count * 3); > + ret = intel_ring_begin(ring, w->count * 4); > if (ret) > return ret; > > @@ -688,6 +688,7 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring) > intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); > intel_ring_emit(ring, w->reg[i].addr); > intel_ring_emit(ring, w->reg[i].value); > + intel_ring_emit(ring, MI_NOOP); > } > > intel_ring_advance(ring); > -- > 2.1.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
