On Thu, Oct 09, 2014 at 08:13:18AM -0700, Jesse Barnes wrote: > Gets the detect code (which may take awhile) out of the resume path, > speeding things up a bit. > > v2: use a delayed work queue instead (Daniel) > v3: cancel delayed work at unload and suspend time (Jesse) > v4: make delayed work comment less scary (Chris) > > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Is this r-b: Chris or not? Two comments below. -Daniel > --- > drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ > drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_drv.h | 1 + > 3 files changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 85d14e1..65001de 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -1303,6 +1303,15 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { > .can_switch = i915_switcheroo_can_switch, > }; > > +static void intel_resume_hotplug(struct work_struct *work) > +{ > + struct drm_i915_private *dev_priv = > + container_of(work, struct drm_i915_private, > + hotplug_resume_work.work); > + > + drm_helper_hpd_irq_event(dev_priv->dev); > +} > + > static int i915_load_modeset_init(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -1364,6 +1373,7 @@ static int i915_load_modeset_init(struct drm_device *dev) > > /* Only enable hotplug handling once the fbdev is fully set up. */ > intel_hpd_init(dev_priv); > + INIT_DELAYED_WORK(&dev_priv->hotplug_resume_work, intel_resume_hotplug); > > /* > * Some ports require correctly set-up hpd registers for detection to > @@ -1854,6 +1864,8 @@ int i915_driver_unload(struct drm_device *dev) > acpi_video_unregister(); > > if (drm_core_check_feature(dev, DRIVER_MODESET)) { > + cancel_delayed_work(&dev_priv->hotplug_resume_work); > + This should be moved to intel_modeset_cleanup to the other hpd quiescent calls imo. Splattering stuff all over isn't good, and if we need to stop hpd handling here already then we should move everything. > intel_fbdev_fini(dev); > intel_modeset_cleanup(dev); > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index a05a1d0..74fc289 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -585,6 +585,12 @@ static int i915_drm_freeze(struct drm_device *dev) > } > > /* > + * In case we haven't run this by the time we resume, we may > + * as well cancel until we resume again. > + */ > + cancel_delayed_work(&dev_priv->hotplug_resume_work); Again this should be right next to the other hpd quiescence calls, i.e. next to drm_kms_helper_poll_disable. > + > + /* > * Disable CRTCs directly since we want to preserve sw state > * for _thaw. Also, power gate the CRTC power wells. > */ > @@ -726,8 +732,17 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) > * notifications. > * */ > intel_hpd_init(dev_priv); > - /* Config may have changed between suspend and resume */ > - drm_helper_hpd_irq_event(dev); > + > + /* > + * Config may have changed between suspend and resume, queue > + * a hotplug notification for userspace to check when it wakes > + * up. Delay the work slightly so that the resume has time to > + * finish, before userspace starts pounding at the gates > + * checking for changes. This speeds up the resume process by > + * reducing contention for resources. > + */ > + schedule_delayed_work(&dev_priv->hotplug_resume_work, > + msecs_to_jiffies(50)); > } > > intel_opregion_init(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1e476b5..6273ad6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1521,6 +1521,7 @@ struct drm_i915_private { > } hpd_stats[HPD_NUM_PINS]; > u32 hpd_event_bits; > struct delayed_work hotplug_reenable_work; > + struct delayed_work hotplug_resume_work; > > struct i915_fbc fbc; > struct i915_drrs drrs; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx