On Thu, Oct 09, 2014 at 07:11:47AM -0700, Rodrigo Vivi wrote: > Let's clean this a bit > > v2: Rebase after other Mika's patch that removed some BDW production workarounds. > v3: Removed stepping info. > > Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 10 ---------- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++--- > 2 files changed, 2 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index daa99e7..23d3318 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5654,16 +5654,6 @@ static void broadwell_init_clock_gating(struct drm_device *dev) > I915_WRITE(WM2_LP_ILK, 0); > I915_WRITE(WM1_LP_ILK, 0); > > - /* FIXME(BDW): Check all the w/a, some might only apply to > - * pre-production hw. */ > - > - > - I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); > - > - I915_WRITE(_3D_CHICKEN3, > - _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); > - > - > /* WaSwitchSolVfFArbitrationPriority:bdw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 816a692..a0c52ad 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -712,13 +712,12 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > return ret; > > /* WaDisablePartialInstShootdown:bdw */ > - /* WaDisableThreadStallDopClockGating:bdw */ > - /* FIXME: Unclear whether we really need this on production bdw. */ > + /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ > intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, > _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE > | STALL_DOP_GATING_DISABLE)); > > - /* WaDisableDopClockGating:bdw May not be needed for production */ > + /* WaDisableDopClockGating:bdw */ > intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
