On Tue, Oct 07, 2014 at 04:11:11PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
>
> Only run it after we actually enable the power well. When we're
> booting the machine there are cases where we run
> hsw_power_well_post_enable without really needing, and even though
> this is not causing any real bugs, it is unneeded and causes confusion
> to people debugging interrupts.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Seems perfectly sensible.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 36749b9..39c33e0 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -221,9 +221,9 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> HSW_PWR_WELL_STATE_ENABLED), 20))
> DRM_ERROR("Timeout enabling power well\n");
> + hsw_power_well_post_enable(dev_priv);
> }
>
> - hsw_power_well_post_enable(dev_priv);
> } else {
> if (enable_requested) {
> I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
> --
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
