On Thu, Oct 02, 2014 at 08:56:54PM +1000, Dave Airlie wrote: > On 2 October 2014 18:40, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote: > >> On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote: > >> > Hey guys, > >> > > >> > so I have a haswell ULT laptop (lenovo t440s), and got access to a > >> > Samsung single panel 4k monitor (no MST). > >> > > >> > Now we detect the monitor fine, but unfortunately the ULT hsw can't > >> > run it over DP, as it has clock limits in place. However we still > >> > offer the 60hz mode and we pick it by default, ensuing black screens. > >> > > >> > I've tested the same monitor with a haswell in a t540p and it works > >> > fine due to having the higher limits in place. > >> > >> We have the IS_HSW_ULX check in intel_dp_max_link_bw, and that's used by > >> both compute_config and mode_valid. So it should work, and from a quick > >> look I don't see any bugs. But obviously something is busted. > >> > >> Can you please printk-augment intel_dp_mode_valid and check what's going > >> wrong there? > > > > Or maybe this is about cdclk instead of link clock? I believe the max > > cdclk ULT can support is 450MHz. I'm not sure if the default would be > > 450MHz or 337.5MHz. Also we still don't have support for changing that > > during runtime even though I regularly try to trick people into > > implementing it. What's the pixel clock of the mode that fails? > > yup it appears to max cdclk, which is 450Mhz on the ULT and 540Mhz on > normal hsw. > > Modeline "3840x2160R" 533.00 3840 3888 3920 4000 2160 2163 2168 > 2222 +hsync -vsync > > cvt gives me that for reduced blank, so around that I guess, I can get > the exact mode line from logs tomorrow if required. Just FYI I went ahead and implemented something for dynamically changing the cdclk frequency on HSW/BDW. But I only have a HSW-ULT on me currently so I couldn't actually test it. While doing that I added cdclk extraction support to all the platforms for which I could find sane docs. For the rest I went with a best guess, which means after my patches we can rely on dev_priv->max_cdclk_freq on all platforms. That should make it trivial to add some .mode_valid() checks based on the max cdclk, but I didn't actually implemnt such checks yet. Here's the code (includes a whole pile of cdclk related stuff) for the brave: git://gitorious.org/vsyrjala/linux.git cdclk_3 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
