On Wed, Oct 01, 2014 at 04:56:56PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Use pack_aux() to construct the PSR exit DPMS D0 AUX message,
> and use the defines from dp_dp_helper.h to populate the message
> contents.
>
> v2: Use sizeof() for message size (Jani)
> Use a generic loop to write EDP_PSR_AUX_DATA registers
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> drivers/gpu/drm/i915/intel_dp.c | 21 ++++++++++++++++-----
> 2 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2e0eb16..09c4af3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2506,9 +2506,7 @@ enum punit_power_well {
>
> #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
> #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
> -#define EDP_PSR_DPCD_COMMAND 0x80060000
> #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
> -#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
> #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
> #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
> #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ad4eb6d..76317ad 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -225,7 +225,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> }
>
> static uint32_t
> -pack_aux(uint8_t *src, int src_bytes)
> +pack_aux(const uint8_t *src, int src_bytes)
> {
> int i;
> uint32_t v = 0;
> @@ -2049,8 +2049,17 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t aux_clock_divider;
> int precharge = 0x3;
> - int msg_size = 5; /* Header(4) + Message(1) */
> bool only_standby = false;
> + static const uint8_t aux_msg[] = {
> + [0] = DP_AUX_NATIVE_WRITE << 4,
> + [1] = DP_SET_POWER >> 8,
> + [2] = DP_SET_POWER & 0xff,
> + [3] = 1 - 1,
> + [4] = DP_SET_POWER_D0,
> + };
> + int i;
> +
> + BUILD_BUG_ON(sizeof(aux_msg) > 20);
>
> aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>
> @@ -2066,11 +2075,13 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
> DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>
> /* Setup AUX registers */
> - I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
> - I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
> + for (i = 0; i < sizeof(aux_msg); i += 4)
> + I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
> + pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
> +
> I915_WRITE(EDP_PSR_AUX_CTL(dev),
> DP_AUX_CH_CTL_TIME_OUT_400us |
> - (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> + (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
> }
> --
> 1.8.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
