[PATCH v2 2/2] drm/i915: Initialize chv workarounds in logical ring mode too

[Michel Thierry <michel.thierry@xxxxxxxxx>]

Also enable the ring->init_context() hook for chv in execlist submission
mode.

For: VIZ-4092
Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 37 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 ++
 3 files changed, 61 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a0aa3f0..7864dac 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1076,6 +1076,39 @@ static int bdw_init_logical_workarounds(struct intel_ringbuffer *ringbuf)
 	return 0;
 }
 
+static int chv_init_logical_workarounds(struct intel_ringbuffer *ringbuf)
+{
+	int ret;
+	struct intel_engine_cs *ring = ringbuf->ring;
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * workarounds applied in this fn are part of register state context,
+	 * they need to be re-initialized followed by gpu reset, suspend/resume,
+	 * module reload.
+	 */
+	dev_priv->num_wa_regs = 0;
+	memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
+
+	/*
+	 * update the number of dwords required based on the
+	 * actual number of workarounds applied
+	 */
+	ret = intel_logical_ring_begin(ringbuf, CHV_WA_DWORDS_SIZE);
+	if (ret)
+		return ret;
+
+	chv_emit_workarounds(ringbuf);
+
+	intel_logical_ring_advance(ringbuf);
+
+	DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
+			 dev_priv->num_wa_regs);
+
+	return 0;
+}
+
 static int gen8_init_common_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -1371,7 +1404,9 @@ static int logical_render_ring_init(struct drm_device *dev)
 	if (HAS_L3_DPF(dev))
 		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-	if (IS_BROADWELL(dev))
+	if (IS_CHERRYVIEW(dev))
+		ring->init_context = chv_init_logical_workarounds;
+	else
 		ring->init_context = bdw_init_logical_workarounds;
 	ring->emit_wa = intel_logical_ring_emit_wa;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e6ac913..ec0b2f0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -776,6 +776,27 @@ static int bdw_init_workarounds(struct intel_ringbuffer *ringbuf)
 	return 0;
 }
 
+void chv_emit_workarounds(struct intel_ringbuffer *ringbuf)
+{
+	struct intel_engine_cs *ring = ringbuf->ring;
+
+	/* WaDisablePartialInstShootdown:chv */
+	ring->emit_wa(ringbuf, GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
+
+	/* WaDisableThreadStallDopClockGating:chv */
+	ring->emit_wa(ringbuf, GEN8_ROW_CHICKEN,
+		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+
+	/* WaDisableDopClockGating:chv (pre-production hw) */
+	ring->emit_wa(ringbuf, GEN7_ROW_CHICKEN2,
+		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
+	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
+	ring->emit_wa(ringbuf, HALF_SLICE_CHICKEN3,
+		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+}
+
 static int chv_init_workarounds(struct intel_ringbuffer *ringbuf)
 {
 	int ret;
@@ -791,25 +812,11 @@ static int chv_init_workarounds(struct intel_ringbuffer *ringbuf)
 	dev_priv->num_wa_regs = 0;
 	memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
 
-	ret = intel_ring_begin(ring, 12);
+	ret = intel_ring_begin(ring, CHV_WA_DWORDS_SIZE);
 	if (ret)
 		return ret;
 
-	/* WaDisablePartialInstShootdown:chv */
-	intel_ring_emit_wa(ringbuf, GEN8_ROW_CHICKEN,
-			   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
-
-	/* WaDisableThreadStallDopClockGating:chv */
-	intel_ring_emit_wa(ringbuf, GEN8_ROW_CHICKEN,
-			   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
-
-	/* WaDisableDopClockGating:chv (pre-production hw) */
-	intel_ring_emit_wa(ringbuf, GEN7_ROW_CHICKEN2,
-			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
-
-	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
-	intel_ring_emit_wa(ringbuf, HALF_SLICE_CHICKEN3,
-			   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+	chv_emit_workarounds(ringbuf);
 
 	intel_ring_advance(ring);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 417aa09..02e3728 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -16,6 +16,7 @@
  * actual number of workarounds applied
  */
 #define BDW_WA_DWORDS_SIZE 18
+#define CHV_WA_DWORDS_SIZE 12
 
 /*
  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
@@ -436,6 +437,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev);
 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
 void intel_ring_setup_status_page(struct intel_engine_cs *ring);
 void bdw_emit_workarounds(struct intel_ringbuffer *ringbuf);
+void chv_emit_workarounds(struct intel_ringbuffer *ringbuf);
 
 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
 {
-- 
2.0.3

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