On Mon, Sep 22, 2014 at 06:22:53PM +0200, Jacek Danecki wrote:
> Current implementation of reading GPU timestamp is broken.
> It returns lower 32 bits shifted by 32 bits (XXXXXXXX00000000 instead of YYYYYYYYXXXXXXXX).
> Below change is adding possibility to read hi part of that register separately.
>
> Signed-off-by: Jacek Danecki jacek.danecki@xxxxxxxxx
Needs to come with corresponding userspace using this.
-Daniel
> ---
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 20673cc..5c87d92 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1089,6 +1089,7 @@ enum punit_power_well {
> #define RING_IMR(base) ((base)+0xa8)
> #define RING_HWSTAM(base) ((base)+0x98)
> #define RING_TIMESTAMP(base) ((base)+0x358)
> +#define RING_TIMESTAMP_HI(base) ((base)+0x35C)
> #define TAIL_ADDR 0x001FFFF8
> #define HEAD_WRAP_COUNT 0xFFE00000
> #define HEAD_WRAP_ONE 0x00200000
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index e81bc3b..6fa4c86 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -969,6 +969,7 @@ static const struct register_whitelist {
> uint32_t gen_bitmask;
> } whitelist[] = {
> { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) },
> + { RING_TIMESTAMP_HI(RENDER_RING_BASE), 4, GEN_RANGE(4, 8) },
> };
>
> int i915_reg_read_ioctl(struct drm_device *dev,
> -- 1.8.3.1
>
> --
> jacek
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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