These registers are used as a temporary storage by MI_MATH command when
performing ALU operations.
Signed-off-by: Michał Winiarski <michal.winiarski@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 4c35e2a..9ad0e69 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -414,6 +414,22 @@ static const u32 gen7_render_regs[] = {
GEN7_3DPRIM_INSTANCE_COUNT,
GEN7_3DPRIM_START_INSTANCE,
GEN7_3DPRIM_BASE_VERTEX,
+ REG64(CS_GPR(0)),
+ REG64(CS_GPR(1)),
+ REG64(CS_GPR(2)),
+ REG64(CS_GPR(3)),
+ REG64(CS_GPR(4)),
+ REG64(CS_GPR(5)),
+ REG64(CS_GPR(6)),
+ REG64(CS_GPR(7)),
+ REG64(CS_GPR(8)),
+ REG64(CS_GPR(9)),
+ REG64(CS_GPR(10)),
+ REG64(CS_GPR(11)),
+ REG64(CS_GPR(12)),
+ REG64(CS_GPR(13)),
+ REG64(CS_GPR(14)),
+ REG64(CS_GPR(15)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8179b..e5e7cca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -461,6 +461,9 @@
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
+/* There are 16 64-bit RCS general purpose registers used by MI_MATH */
+#define CS_GPR(n) (0x2600 + (n) * 8)
+
#define GEN7_3DPRIM_END_OFFSET 0x2420
#define GEN7_3DPRIM_START_VERTEX 0x2430
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
--
1.9.3
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