From: Yu Zhang <yu.c.zhang@xxxxxxxxx>
In the virtualized environment, forcewake operations are not
necessory for the driver, because mmio accesses will be trapped
and emulated by the host side, and real forcewake operations are
also done in the host. New mmio write handlers are added to directly
call the __raw_i915_write, therefore will reduce many traps and
increase the overall performance for drivers runing in the VM
with Intel GVT-g enhancement
Signed-off-by: Yu Zhang <yu.c.zhang@xxxxxxxxx>
Signed-off-by: Jike Song <jike.song@xxxxxxxxx>
Signed-off-by: Kevin Tian <kevin.tian@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_dma.c | 7 +++++--
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 24 ++++++++++++++++++++++++
3 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d9462e1..a3fe7c0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1741,10 +1741,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
i915_check_vgpu(dev);
- /* disable framebuffer compression in vgt */
- if (intel_vgpu_active(dev))
+ if (intel_vgpu_active(dev)) {
+ /* disable framebuffer compression in vgt */
i915.enable_fbc = 0;
+ intel_vgpu_reg_write_init(dev);
+ }
+
intel_irq_init(dev);
intel_uncore_sanitize(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caae6ed..c891638 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2334,6 +2334,7 @@ extern void intel_uncore_fini(struct drm_device *dev);
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
extern void i915_check_vgpu(struct drm_device *dev);
+extern void intel_vgpu_reg_write_init(struct drm_device *dev);
static inline bool intel_vgpu_active(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 918b761..87f2a69 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -722,6 +722,14 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
REG_WRITE_FOOTER; \
}
+#define __vgpu_write(x) \
+static void \
+vgpu_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+ REG_WRITE_HEADER; \
+ __raw_i915_write##x(dev_priv, reg, val); \
+ REG_WRITE_FOOTER; \
+}
+
static const u32 gen8_shadowed_regs[] = {
FORCEWAKE_MT,
GEN6_RPNSWREQ,
@@ -816,6 +824,10 @@ __gen4_write(8)
__gen4_write(16)
__gen4_write(32)
__gen4_write(64)
+__vgpu_write(8)
+__vgpu_write(16)
+__vgpu_write(32)
+__vgpu_write(64)
#undef __chv_write
#undef __gen8_write
@@ -823,9 +835,21 @@ __gen4_write(64)
#undef __gen6_write
#undef __gen5_write
#undef __gen4_write
+#undef __vgpu_write
#undef REG_WRITE_FOOTER
#undef REG_WRITE_HEADER
+void intel_vgpu_reg_write_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ dev_priv->uncore.funcs.mmio_writeb = vgpu_write8;
+ dev_priv->uncore.funcs.mmio_writew = vgpu_write16;
+ dev_priv->uncore.funcs.mmio_writel = vgpu_write32;
+ dev_priv->uncore.funcs.mmio_writeq = vgpu_write64;
+
+}
+
void intel_uncore_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
--
1.9.1
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