On Thu, Sep 18, 2014 at 05:58:32PM +0300, Mika Kuoppala wrote: > Render context on gen8 is not guaranteed to be loaded (active) > at the instant when forcewake ack shows up. So we need extra > steps to get it in before we access specific registers. > > We could do register white listing to do the extra dance only on > specific render context access. However the main concern is > is ring initialization after reset/resume, so only take the extra > steps on user forcewake as it is already guarding ring init. And not incur > extra perf penalty to regular register accesses. This allows us to be > sure that we don't read all zeros on RMW cycles. And we to show a > consistent state to igt when user fw has been acquired. Might I just ask why? This talks about the need to serialise with the LRI use to load the context registers, so be explicit. When reading those registers, we should know what is going on with the GPU or just don't care. Writing to those registers once the ring is running is verboten. This is just very thin papering over an unexplained problem. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
