On Thu, Sep 18, 2014 at 05:23:14PM +0300, Imre Deak wrote: > On Thu, 2014-09-18 at 14:56 +0100, Damien Lespiau wrote: > > > > #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ > > > > BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > > > > BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > > > > + BIT(POWER_DOMAIN_AUX_B) | \ > > > > BIT(POWER_DOMAIN_INIT)) > > > > > > > > #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ > > > > BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > > > > + BIT(POWER_DOMAIN_AUX_B) | \ > > > > BIT(POWER_DOMAIN_INIT)) > > > > Wouldn't it better to leave the AUX domain in the LANES_01 power domain, > > otherwise we'll power up the full 4 lanes for aux transactions? > > With this patch I thought that we'd keep things as-is for all platforms > except SKL. I imagined that we'd get only the AUX power domains for AUX > functionality (in patch 72/89) and not take the port power domains for > full port functionality. That would provide the extra power saving on > SKL and would keep the other platforms unchanged. > > You are right that we probably don't need the TX power wells for AUX > functionality on VLV, but I haven't checked this yet, so this would need > to be done separately as a follow-up. And we always have the nasty CMN vs. TX ordering issue on VLV. So unless someone adds the logic to bring the wells down and back up again when we need to power up TX wells when CMN is already up, we just have to keep TX wells powered whenever CMN is powered. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
