In our suspend/resume and driver load code we enable power wells and interrupts in different order than with runtime pm, which means code needs to check for that and act accordingly. Unfortunately with the SOiX support the "are interrupts enabled" checks went out of sync. Fix up more places. This specific one was caught by the recently added interrupt checks in pipestate_enable/disable functions. This resulted in the following backtrace Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. Suspending console(s) (use no_console_suspend to debug) sd 0:0:0:0: [sda] Synchronizing SCSI cache sd 0:0:0:0: [sda] Stopping disk ------------[ cut here ]------------ WARNING: CPU: 1 PID: 20572 at drivers/gpu/drm/i915/i915_irq.c:619 i915_disable_pipestat+0x94/0x122 [i915]() Modules linked in: dm_mod iTCO_wdt iTCO_vendor_support snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep pcspkr snd_pcm serio_raw snd_timer i2c_i801 lpc_ich snd mfd_core soundcore iosf_mbi battery ac acpi_cpufreq i915 button video drm_kms_helper drm CPU: 1 PID: 20572 Comm: kworker/u8:2 Tainted: G W 3.17.0-rc4_prts_a44085_20140912_debug+ #62 Workqueue: events_unbound async_run_entry_fn 0000000000000000 ffff88006f0dbb18 ffffffff81815c9c 0000000000000000 ffff88006f0dbb50 ffffffff8103e87f ffffffffa00b32e1 ffff880003690000 0000000000001c00 000000001c000000 00000000001f0024 ffff88006f0dbb60 Call Trace: [] dump_stack+0x45/0x56 [] warn_slowpath_common+0x7f/0x98 [] ? i915_disable_pipestat+0x94/0x122 [i915] [] warn_slowpath_null+0x1a/0x1c [] i915_disable_pipestat+0x94/0x122 [i915] [] valleyview_display_irqs_uninstall+0x99/0x101 [i915] [] valleyview_disable_display_irqs+0x37/0x39 [i915] [] vlv_display_power_well_disable+0x53/0x79 [i915] [] intel_display_power_put+0xe3/0x111 [i915] [] intel_display_set_init_power+0x31/0x3d [i915] [] i915_drm_freeze+0x1c0/0x1cd [i915] [] i915_pm_suspend+0x44/0x46 [i915] [] pci_pm_suspend+0x85/0x106 [] ? pci_pm_freeze+0xb1/0xb1 [] dpm_run_callback+0x43/0xd3 [] __device_suspend+0x1e3/0x263 [] async_suspend+0x1f/0x8a [] async_run_entry_fn+0x61/0x10b [] process_one_work+0x221/0x3f2 [] ? process_one_work+0x1ac/0x3f2 [] worker_thread+0x288/0x37c [] ? cancel_delayed_work_sync+0x15/0x15 [] kthread+0xf6/0xfe [] ? kthread_create_on_node+0x19a/0x19a [] ret_from_fork+0x7c/0xb0 [] ? kthread_create_on_node+0x19a/0x19a ---[ end trace f0b4cc6544a9afea ]--- Cc: Imre Deak <imre.deak@xxxxxxxxx> Cc: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7db0029558a4..20a5d6150919 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3723,7 +3723,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) dev_priv->display_irqs_enabled = true; - if (dev_priv->dev->irq_enabled) + if (dev_priv->pm._irqs_disabled) valleyview_display_irqs_install(dev_priv); } @@ -3736,7 +3736,7 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) dev_priv->display_irqs_enabled = false; - if (dev_priv->dev->irq_enabled) + if (dev_priv->pm._irqs_disabled) valleyview_display_irqs_uninstall(dev_priv); } -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
