On Thu, Sep 11, 2014 at 01:54:44PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate > exceeds 95% of the core display clock. Apparently this can cause > underruns. > > There's no similar restriction listed for HSW, so leave that one alone > for now. > > Tested-by: Timo Aaltonen <tjaalton@xxxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 10 ++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 16 +++++++--------- > 3 files changed, 16 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 965eb3c..ca729e5 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5244,9 +5244,15 @@ retry: > static void hsw_compute_ips_config(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config) > { > + struct drm_device *dev = crtc->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + > pipe_config->ips_enabled = i915.enable_ips && > - hsw_crtc_supports_ips(crtc) && > - pipe_config->pipe_bpp <= 24; > + hsw_crtc_supports_ips(crtc) && > + pipe_config->pipe_bpp <= 24 && > + (IS_HASWELL(dev) || > + ilk_pipe_pixel_rate(pipe_config) <= > + 95 * intel_ddi_get_cdclk_freq(dev_priv) / 100); Could you wrap this up neatly with pipe_config_supports_ips(dev_priv, pipe_config) ? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
