On Fri, Sep 05, 2014 at 01:53:12PM +0100, Damien Lespiau wrote:
> Ville found out that the DATA1 register exists since SNB with some
> scarce apparitions in the specs throughout the times. In his own words:
>
> Also according to Bspec the mailbox data1 register already existed
> since snb. The hsw cdclk change sequence also mentions that it should
> be set to 0, but eg. the bdw IPS sequence doesn't mention it. I guess
> in theory some pcode command might cause it to be clobbered, so I'm
> thinking we should just explicitly set it to 0 for all platforms in
> the pcode read/write functions
>
> Suggested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 3 +--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5a7adb1..56cccde 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5952,8 +5952,8 @@ enum skl_disp_power_wells {
> #define GEN6_PCODE_DATA 0x138128
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
> +#define GEN6_PCODE_DATA1 0x13812C
>
> -#define GEN9_PCODE_DATA1 0x13812C
> #define GEN9_PCODE_READ_MEM_LATENCY 0x6
> #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
> #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3f69f9a..7bc8f73 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8716,8 +8716,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
> }
>
> I915_WRITE(GEN6_PCODE_DATA, *val);
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> - I915_WRITE(GEN9_PCODE_DATA1, 0);
> + I915_WRITE(GEN6_PCODE_DATA1, 0);
> I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
>
> if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
> --
> 1.8.3.1
--
Ville Syrjälä
Intel OTC
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