On Wed, Sep 10, 2014 at 03:25:31PM +0200, Thomas Richter wrote:
> Am 10.09.2014 14:22, schrieb Daniel Vetter:
> > On Wed, Sep 10, 2014 at 02:17:30PM +0200, Thomas Richter wrote:
> >> Hi Daniel, hi Ville,
> >>
> >> just tried the new 3.17.0+rc4 kernel, though with old userspace (i.e.
> >> xserver-xorg-video-intel is *old*, libdrm is old, mesa is old). If I do, I
> >> get a "GPU hung" from xorg.conf. The same userspace works fine on 3.15.0
> >> with patches from Ville.
> >>
> >> Is this expected behavior or should I open up a bug report (I have dmesg
> >> output and debugging output from DRI ready on this, but it's a bith
> >> lengthy.)
> > Please retest with latest drm-intel-nightly, if just merged a patch from
> > Chris to prevent gpu hangs on i830/i845. If it still blows up please
> > attach and error state captured from that kernel.
> No, not merged from a patch. This is a clean checkout of "master".
> drm-intel-nightly did not contain the watermark fixes
> the last time I checked. Error state is attached. I put Chris into CC.
The w/a batch is corrupted. 0x400-0x1000 somehow got turned into zeroes.
Both are page boundaries, so I guess trying out Chris's TLB fix would
be worth a shot.
This is the commit you want:
commit c4d69da167fa967749aeb70bc0e94a457e5d00c1
Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Date: Mon Sep 8 14:25:41 2014 +0100
drm/i915: Evict CS TLBs between batches
I just trawled through BSpec a bit and I see a clear note there that BLT
TLBs are hosed on 830/845 and we need to flush after touching PTEs so
that BLT will see the correct stuff. There's also a note that touching
PGETBL_CTL enable bit would also flush all TLBs. So I wonder if just
I915_WRITE(PGETBL_CTL, I915_READ(PGETBL_CTL)) after touching the PTEs
would be enough to eliminate this problem?
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
