On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote: > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with > the security bit (i.e. only privileged batches were allowed to run from > ggtt). From Haswell onwards, you are able to select the security bit ggtt). For Haswell only, you are able to select the security bit > separate from the address space - and we always requested to use ppgtt. > This breaks the golden render state batch execution with full-ppgtt as > that is only present in the global GTT and more generally any secure > batch that is not colocated in the ppgtt and ggtt. So we need to > disable the use of the ppgtt selector bit for secure batches, or else we > hang immediately upon boot and thence after every GPU reset... > > v2: Only HSW differentiates between secure dispatch and ggtt, so simply > ignore the differentiation and always use secure==ggtt. > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 109de2eeb9a8..25795f2efdcb 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2203,8 +2203,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, > return ret; > > intel_ring_emit(ring, > - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | > - (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); > + MI_BATCH_BUFFER_START | > + (flags & I915_DISPATCH_SECURE ? > + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); > /* bit0-7 is the length on GEN6+ */ > intel_ring_emit(ring, offset); > intel_ring_advance(ring); > -- > 2.1.0 > -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
