On Tue, Sep 09, 2014 at 11:25:13AM +0300, Jani Nikula wrote: > eDP panels are generally designed to support only a single clock and > lane configuration. > > commit 56071a207602a451f0c46d3dcc8379b59ef576e2 > Author: Jani Nikula <jani.nikula@xxxxxxxxx> > Date: Tue May 6 14:56:52 2014 +0300 > > drm/i915: use lane count and link rate from VBT as minimums for eDP > > should have started using the optimal link parameters for eDP > panels. Turns out a certain other OS uses DPCD instead of VBT, which > means trusting VBT on this may not be so reliable after all. Follow > suit. Oh well, let's dare the edp lords a bit and merge this to dinq. /me closes the hatch of the bunker and hunxches down > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81647 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79386 Please add the Tested-by: lines gathered from bugzilla next time around. I've fixed that. > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> Thanks, Daniel > --- > drivers/gpu/drm/i915/intel_dp.c | 26 +++++++++----------------- > 1 file changed, 9 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index ab7cd0a75bd5..72bf533596c8 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1068,23 +1068,15 @@ intel_dp_compute_config(struct intel_encoder *encoder, > bpp = dev_priv->vbt.edp_bpp; > } > > - if (IS_BROADWELL(dev)) { > - /* Yes, it's an ugly hack. */ > - min_lane_count = max_lane_count; > - DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", > - min_lane_count); > - } else if (dev_priv->vbt.edp_lanes) { > - min_lane_count = min(dev_priv->vbt.edp_lanes, > - max_lane_count); > - DRM_DEBUG_KMS("using min %u lanes per VBT\n", > - min_lane_count); > - } > - > - if (dev_priv->vbt.edp_rate) { > - min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); > - DRM_DEBUG_KMS("using min %02x link bw per VBT\n", > - bws[min_clock]); > - } > + /* > + * Use the maximum clock and number of lanes the eDP panel > + * advertizes being capable of. The panels are generally > + * designed to support only a single clock and lane > + * configuration, and typically these values correspond to the > + * native resolution of the panel. > + */ > + min_lane_count = max_lane_count; > + min_clock = max_clock; > } > > for (; bpp >= 6*3; bpp -= 2*3) { > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
