On Fri, Sep 05, 2014 at 11:42:32AM +0300, Ville Syrjälä wrote: > On Fri, Sep 05, 2014 at 09:29:33AM +0100, Damien Lespiau wrote: > > On Fri, Sep 05, 2014 at 11:25:30AM +0300, Ville Syrjälä wrote: > > > > +/* SKL GT Driver Mailbox registers for reading memory latencies */ > > > > +#define GEN9_MAILBOX_DATA1 0x13812C > > > > +#define GEN9_MAILBOX_READ_MEM_LAT (0x6) > > > > +#define GEN9_MAILBOX_READ_TIMEOUT 150 > > > > > > Timeout not used anywhere. Also spec says 100us. > > > > > > > +#define GEN9_MEM_LAT_LEVEL_MASK 0xFF > > > > +#define GEN9_MEM_LAT_LEVEL_1_5_SHIFT 8 > > > > +#define GEN9_MEM_LAT_LEVEL_2_6_SHIFT 16 > > > > +#define GEN9_MEM_LAT_LEVEL_3_7_SHIFT 24 > > > > > > This stuff should be grouped along the other pcode register defines. > > > > Funny you mention this, I fixed those two in the v6 sent as reply > > yesterday. > > Well that's two down then. The other 2 items were marked as "patch on top is fine/better", so I guess it's now r-b material? In any case, addressed the 2 points you raised separately. http://lists.freedesktop.org/archives/intel-gfx/2014-September/052008.html -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
