On Thu, Sep 4, 2014 at 12:55 AM, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote:This idle frame detection still depends of FBC right?
> With Software tracking we are going to PSR sooner than we should and staying
> with blank screens in many cases.
>
> Using 2 identical frames to detect idleness is safier.
not sure. and fbc is disabled anyway here on my tests.
I believe if we want to go for full sw tracking on HSW/BDW we need to
use the debug register to force PSR entry/exit.
I tried this many times in different ways but never had success
--
>
> Discovered and validated with refactored igt/kms_sink_psr_crc.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f79473b..a796831 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t max_sleep_time = 0x1f;
> - uint32_t idle_frames = 1;
> + uint32_t idle_frames = 2;
> uint32_t val = 0x0;
> const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> bool _only_standby_ = false;
> --
> 1.9.3
>
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Ville Syrjälä
Intel OTC
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Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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