On Thu, Sep 4, 2014 at 6:24 PM, Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote: > On Thu, 4 Sep 2014 17:59:18 +0200 > Daniel Vetter <daniel.vetter@xxxxxxxx> wrote: > >> On Thu, Aug 28, 2014 at 1:00 AM, Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote: >> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> >> index 9eb303c1b621..76bc4d0de5a4 100644 >> >> --- a/drivers/gpu/drm/i915/i915_irq.c >> >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> >> @@ -589,6 +589,7 @@ __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, >> >> u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; >> >> >> >> assert_spin_locked(&dev_priv->irq_lock); >> >> + WARN_ON(!intel_irqs_enabled(dev_priv)); >> >> >> >> if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || >> >> status_mask & ~PIPESTAT_INT_STATUS_MASK, >> >> @@ -615,6 +616,7 @@ __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, >> >> u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; >> >> >> >> assert_spin_locked(&dev_priv->irq_lock); >> >> + WARN_ON(!intel_irqs_enabled(dev_priv)); >> >> >> >> if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || >> >> status_mask & ~PIPESTAT_INT_STATUS_MASK, >> > >> > Yeah looks good, wonder if it'll trigger any new warnings. >> >> It will blow up in a bunch of postinstall hooks, just like the one for >> ilk. At least without my patch to shuffle the pm._irqs_disabled >> assignment around. >> >> > Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> >> >> ... so does that count as an implicit r-b on my other patch? > > Sure, though didn't Jani find some issues with it? QA claims that both my and your patch break the display on hsw, bdw and snb or something like that. Which either means I'm blind (since either patch should only affect ilk in a functional way) or they're doing something really strange. I have no idea what's actually going on there, but we have a regular stream of reports of this one here ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
