On Thu, Aug 07, 2014 at 07:05:49PM +0300, Ville Syrjälä wrote: > On Thu, Aug 07, 2014 at 03:39:54PM +0100, Chris Wilson wrote: > > Ville found an old w/a documented for g4x that suggested that we need to > > reset the HEAD after writing START. This is a useful fixup for some of > > the g4x ring initialisation woes, but as usual, not all. > > > > v2: Do the rewrite unconditionally anyway > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=76554 > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Yeah looks sensible to me. So based on my gut feeling just from the > seeing the w/a name this is: > > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. Although if a tested-by shows up we should really throw this one into -fixes, since the current duct-tape still seems to be less effective than whatever kept things working previously. -Daniel > > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 45e3ec927051..26ec25afc02a 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -537,6 +537,14 @@ static int init_ring_common(struct intel_engine_cs *ring) > > * also enforces ordering), otherwise the hw might lose the new ring > > * register values. */ > > I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); > > + > > + /* WaClearRingBufHeadRegAtInit:ctg,elk */ > > + if (I915_READ_HEAD(ring)) > > + DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", > > + ring->name, I915_READ_HEAD(ring)); > > + I915_WRITE_HEAD(ring, 0); > > + (void)I915_READ_HEAD(ring); > > + > > I915_WRITE_CTL(ring, > > ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) > > | RING_VALID); > > -- > > 2.1.0.rc1 > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
