On Fri, Aug 22, 2014 at 02:06:04PM +0530, sonika.jindal@xxxxxxxxx wrote:
> From: Sonika Jindal <sonika.jindal@xxxxxxxxx>
>
> Primary planes support 180 degree rotation. Expose the feature
> through rotation drm property.
>
> v2: Calculating linear/tiled offsets based on pipe source width and
> height. Added 180 degree rotation support in ironlake_update_plane.
>
> v3: Checking if CRTC is active before issueing update_plane. Added
> wait for vblank to make sure we dont overtake page flips. Disabling
> FBC since it does not work with rotated planes.
>
> v4: Updated rotation checks for pending flips, fbc disable. Creating
> rotation property only for Gen4 onwards. Property resetting as part
> of lastclose.
>
> v5: Resetting property in i915_driver_lastclose properly for planes
> and crtcs. Fixed linear offset calculation that was off by 1 w.r.t
> width in i9xx_update_plane and ironlake_update_plane. Removed tab
> based indentation and unnecessary braces in intel_crtc_set_property
> and intel_update_fbc. FBC and flip related checks should be done only
> for valid crtcs.
>
> v6: Minor nits in FBC disable checks for comments in intel_crtc_set_property
> and positioning the disable code in intel_update_fbc.
>
> v7: In case rotation property on inactive crtc is updated, we return
> successfully printing debug log as crtc is inactive and only property change
> is preserved.
>
> v8: update_plane is changed to update_primary_plane, crtc->fb is changed to
> crtc->primary->fb and return value of update_primary_plane is ignored.
>
> v9: added rotation property to primary plane instead of crtc. Removing reset
> of rotation property from lastclose. rotation_property is moved to
> drm_mode_config, so drm layer will take care of resetting. Adding updation of
> fbc when rotation is set to 0. Allowing rotation only if value is
> different than old one.
>
> v10: Calling intel_primary_plane_setplane instead of update_primary_plane in
> set_property(Daniel).
>
> v11: Using same set_property function for both primary and sprite, Adding
> primary plane specific code in the same function (Matt).
>
> v12: Removing disabling/ enabling of fbc from set_property because it is done
> from intel_pipe_set_base. Other formatting
>
> v13: we need to call disable_fbc before changing the rotation to 180,
> disable_fbc from intel_pipe_set_base gets called very late, that will
> be used to re-enable fbc if rotation is set to 0 (Ville).
>
> Testcase: igt/kms_rotation_crc
>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Sagar Kamble <sagar.a.kamble@xxxxxxxxx>
> Signed-off-by: Sonika Jindal <sonika.jindal@xxxxxxxxx>
Queued for -next, thanks for the patch. I've added a FIXME to the
disable_fbc so that we know there's some work left to do in the future.
And I've polished the coding style a bit in some places (function argument
alignement, comment style and folding int some nested if clauses).
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 69 ++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_drv.h | 3 ++
> drivers/gpu/drm/i915/intel_pm.c | 6 +++
> drivers/gpu/drm/i915/intel_sprite.c | 4 +-
> 5 files changed, 77 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 203062e..142ac52 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4214,6 +4214,7 @@ enum punit_power_well {
> #define DISPPLANE_NO_LINE_DOUBLE 0
> #define DISPPLANE_STEREO_POLARITY_FIRST 0
> #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
> +#define DISPPLANE_ROTATE_180 (1<<15)
> #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
> #define DISPPLANE_TILED (1<<10)
> #define _DSPAADDR 0x70184
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f2a8797..0c77438 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2384,6 +2384,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> unsigned long linear_offset;
> u32 dspcntr;
> u32 reg = DSPCNTR(plane);
> + int pixel_size;
> +
> + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
>
> if (!intel_crtc->primary_enabled) {
> I915_WRITE(reg, 0);
> @@ -2450,8 +2453,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> if (IS_G4X(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - I915_WRITE(reg, dspcntr);
> -
> linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> @@ -2464,6 +2465,21 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> intel_crtc->dspaddr_offset = linear_offset;
> }
>
> + if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
> + dspcntr |= DISPPLANE_ROTATE_180;
> +
> + x += (intel_crtc->config.pipe_src_w - 1);
> + y += (intel_crtc->config.pipe_src_h - 1);
> +
> + /* Finding the last pixel of the last line of the display
> + data and adding to linear_offset*/
> + linear_offset +=
> + (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
> + (intel_crtc->config.pipe_src_w - 1) * pixel_size;
> + }
> +
> + I915_WRITE(reg, dspcntr);
> +
> DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
> i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
> fb->pitches[0]);
> @@ -2490,6 +2506,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> unsigned long linear_offset;
> u32 dspcntr;
> u32 reg = DSPCNTR(plane);
> + int pixel_size;
> +
> + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
>
> if (!intel_crtc->primary_enabled) {
> I915_WRITE(reg, 0);
> @@ -2538,14 +2557,28 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - I915_WRITE(reg, dspcntr);
> -
> linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> intel_crtc->dspaddr_offset =
> intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
> fb->bits_per_pixel / 8,
> fb->pitches[0]);
> linear_offset -= intel_crtc->dspaddr_offset;
> + if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
> + dspcntr |= DISPPLANE_ROTATE_180;
> +
> + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> + x += (intel_crtc->config.pipe_src_w - 1);
> + y += (intel_crtc->config.pipe_src_h - 1);
> +
> + /* Finding the last pixel of the last line of the display
> + data and adding to linear_offset*/
> + linear_offset +=
> + (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
> + (intel_crtc->config.pipe_src_w - 1) * pixel_size;
> + }
> + }
> +
> + I915_WRITE(reg, dspcntr);
>
> DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
> i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
> @@ -11572,6 +11605,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
> uint32_t src_w, uint32_t src_h)
> {
> struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
> @@ -11684,6 +11718,18 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
> mutex_unlock(&dev->struct_mutex);
>
> } else {
> + if (intel_crtc && intel_crtc->active &&
> + intel_crtc->primary_enabled) {
> +
> + /* FBC does not work on some platforms for rotated
> + planes, so disable it when rotation is not 0 and update
> + it when rotation is set back to 0 */
> + if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) {
> + if (dev_priv->fbc.plane == intel_crtc->plane &&
> + intel_plane->rotation != BIT(DRM_ROTATE_0))
> + intel_disable_fbc(dev);
> + }
> + }
> ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
> if (ret)
> return ret;
> @@ -11717,6 +11763,7 @@ static const struct drm_plane_funcs intel_primary_plane_funcs = {
> .update_plane = intel_primary_plane_setplane,
> .disable_plane = intel_primary_plane_disable,
> .destroy = intel_plane_destroy,
> + .set_property = intel_plane_set_property
> };
>
> static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> @@ -11734,6 +11781,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> primary->max_downscale = 1;
> primary->pipe = pipe;
> primary->plane = pipe;
> + primary->rotation = BIT(DRM_ROTATE_0);
> if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
> primary->plane = !pipe;
>
> @@ -11749,6 +11797,19 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> &intel_primary_plane_funcs,
> intel_primary_formats, num_formats,
> DRM_PLANE_TYPE_PRIMARY);
> +
> + if (INTEL_INFO(dev)->gen >= 4) {
> + if (!dev->mode_config.rotation_property)
> + dev->mode_config.rotation_property =
> + drm_mode_create_rotation_property(dev,
> + BIT(DRM_ROTATE_0) |
> + BIT(DRM_ROTATE_180));
> + if (dev->mode_config.rotation_property)
> + drm_object_attach_property(&primary->base.base,
> + dev->mode_config.rotation_property,
> + primary->rotation);
> + }
> +
> return &primary->base;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d683a20..3e5d6b3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1093,6 +1093,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
> int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
> enum plane plane);
> +int intel_plane_set_property(struct drm_plane *plane,
> + struct drm_property *prop,
> + uint64_t val);
> int intel_plane_restore(struct drm_plane *plane);
> void intel_plane_disable(struct drm_plane *plane);
> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c8f744c..1ab3e11 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -581,6 +581,12 @@ void intel_update_fbc(struct drm_device *dev)
> DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
> goto out_disable;
> }
> + if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
> + to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
> + if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
> + DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
> + goto out_disable;
> + }
>
> /* If the kernel debugger is active, always disable compression */
> if (in_dbg_master())
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0bdb00b..be9bc21 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1218,7 +1218,7 @@ out_unlock:
> return ret;
> }
>
> -static int intel_plane_set_property(struct drm_plane *plane,
> +int intel_plane_set_property(struct drm_plane *plane,
> struct drm_property *prop,
> uint64_t val)
> {
> @@ -1249,7 +1249,7 @@ int intel_plane_restore(struct drm_plane *plane)
> if (!plane->crtc || !plane->fb)
> return 0;
>
> - return intel_update_plane(plane, plane->crtc, plane->fb,
> + return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
> intel_plane->crtc_x, intel_plane->crtc_y,
> intel_plane->crtc_w, intel_plane->crtc_h,
> intel_plane->src_x, intel_plane->src_y,
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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