From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> Because BDW has WPT, which is equivalent to LPT. This is just like the CPT/PPT case. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c8f744c..b3e948f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5595,6 +5595,8 @@ static void gen8_init_clock_gating(struct drm_device *dev) /* Wa4x4STCOptimizationDisable:bdw */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); + + lpt_init_clock_gating(dev); } static void haswell_init_clock_gating(struct drm_device *dev) -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
