2014-08-14 13:51 GMT-03:00 <arun.siluvery@xxxxxxxxxxxxxxx>:
> From: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
>
> This patch adds a new test to verify applied workarounds before
> and after an operation such as gpu reset, suspend/resume.
>
> It is a simple test which captures w/a state at the beginning and
> compares their status with the state after the operation.
>
> v2: w/a table is removed from igt as driver exports it via debugfs file.
It would be good if you could also add a test to check if the
woarkarounds survive runtime PM.
>
> Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> ---
> tests/Makefile.sources | 1 +
> tests/gem_workarounds.c | 252 ++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 253 insertions(+)
> create mode 100644 tests/gem_workarounds.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0eb9369..e16e22a 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -62,6 +62,7 @@ TESTS_progs_M = \
> gem_tiled_partial_pwrite_pread \
> gem_userptr_blits \
> gem_write_read_ring_switch \
> + gem_workarounds \
> kms_addfb \
> kms_cursor_crc \
> kms_fbc_crc \
> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
> new file mode 100644
> index 0000000..cac1027
> --- /dev/null
> +++ b/tests/gem_workarounds.c
> @@ -0,0 +1,252 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + * Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> + *
> + */
> +
> +#define _GNU_SOURCE
> +#include <stdbool.h>
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <fcntl.h>
> +#include <inttypes.h>
> +#include <errno.h>
> +#include <sys/stat.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <time.h>
> +#include <signal.h>
> +
> +#include "ioctl_wrappers.h"
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_aux.h"
> +#include "intel_chipset.h"
> +#include "intel_io.h"
> +
> +enum operation {
> + GPU_RESET = 0x01,
> + SUSPEND_RESUME = 0x02,
> +};
> +
> +struct intel_wa {
> + uint32_t addr;
> + uint32_t value;
> + uint32_t mask;
> +};
> +
> +int drm_fd;
> +uint32_t devid;
> +static drm_intel_bufmgr *bufmgr;
> +struct intel_batchbuffer *batch;
> +int num_wa;
> +struct intel_wa *workarounds;
> +
> +
> +static void test_hang_gpu(void)
> +{
> + int retry_count = 30;
> + enum stop_ring_flags flags;
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 gem_exec;
> + uint32_t b[2] = {MI_BATCH_BUFFER_END};
> +
> + igt_assert(retry_count);
> + igt_set_stop_rings(STOP_RING_DEFAULTS);
> +
> + memset(&gem_exec, 0, sizeof(gem_exec));
> + gem_exec.handle = gem_create(drm_fd, 4096);
> + gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = (uintptr_t)&gem_exec;
> + execbuf.buffer_count = 1;
> + execbuf.batch_len = sizeof(b);
> +
> + drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
> +
> + while(retry_count--) {
> + flags = igt_get_stop_rings();
> + if (flags == 0)
> + break;
> + printf("gpu hang not yet cleared, retries left %d\n", retry_count);
> + sleep(1);
> + }
> +
> + flags = igt_get_stop_rings();
> + if (flags)
> + igt_set_stop_rings(STOP_RING_NONE);
> +}
> +
> +static void test_suspend_resume(void)
> +{
> + printf("Suspending the device ...\n");
> + igt_system_suspend_autoresume();
> +}
> +
> +static void capture_wa_state(const char *wa_reg_file, char *buf, int size)
> +{
> + int fd;
> + int len = 0;
> + char data[512];
> +
> + fd = igt_debugfs_open(wa_reg_file, O_RDONLY);
> + igt_assert(fd > 0);
> + len = read(fd, data, size);
> + data[len - 1] = '\0';
> + close(fd);
> +
> +}
> +
> +static void get_current_wa_data(struct intel_wa **curr, int num)
> +{
> + int i;
> + struct intel_wa *ptr = NULL;
> +
> + ptr = *curr;
> +
> + intel_register_access_init(intel_get_pci_device(), 0);
> +
> + for (i = 0; i < num; ++i) {
> + ptr[i].addr = workarounds[i].addr;
> + ptr[i].value = intel_register_read(workarounds[i].addr);
> + ptr[i].mask = workarounds[i].mask;
> + }
> +
> + intel_register_access_fini();
> +}
> +
> +static void check_workarounds(enum operation op, int num)
> +{
> + int i;
> + int fail_count = 0;
> + int status = 0;
> + struct intel_wa *current_wa = NULL;
> +
> + switch (op) {
> + case GPU_RESET:
> + test_hang_gpu();
> + break;
> +
> + case SUSPEND_RESUME:
> + test_suspend_resume();
> + break;
> +
> + default:
> + fail_count = 1;
> + goto out;
> + }
> +
> + current_wa = malloc(num * sizeof(*current_wa));
> + igt_assert(current_wa);
> + get_current_wa_data(¤t_wa, num);
> +
> + printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
> + for (i = 0; i < num; ++i) {
> + status = (current_wa[i].value & current_wa[i].mask) !=
> + (workarounds[i].value & workarounds[i].mask);
> + if (status)
> + ++fail_count;
> +
> + printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
> + current_wa[i].addr, workarounds[i].value,
> + current_wa[i].value, current_wa[i].mask,
> + status ? "fail" : "success");
> + }
> +
> +out:
> + free(current_wa);
> + igt_assert(fail_count == 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + igt_subtest_init(argc, argv);
> +
> + igt_fixture {
> + int i;
> + int ret;
> + FILE *file;
> + int card_index;
> + const char *dri_path = "/sys/kernel/debug/dri";
> + char *filename = NULL;
> + char *line = NULL;
> + size_t line_size;
> +
> + drm_fd = drm_open_any();
> +
> + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> + devid = intel_get_drm_devid(drm_fd);
> + batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> + card_index = drm_get_card();
> + igt_assert(card_index != -1);
> +
> + ret = asprintf(&filename, "%s/%d/intel_wa_registers",
> + dri_path, card_index);
> + igt_assert(ret > 0);
> +
> + file = fopen(filename, "r");
> + igt_assert(file > 0);
> +
> + ret = getline(&line, &line_size, file);
> + igt_assert(ret > 0);
> + sscanf(line, "Workarounds applied: %d", &num_wa);
> + igt_assert(num_wa > 0);
> +
> + workarounds = malloc(num_wa * sizeof(*workarounds));
> +
> + i = 0;
> + while(getline(&line, &line_size, file) > 0) {
> + sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
> + &workarounds[i].addr, &workarounds[i].value,
> + &workarounds[i].mask);
> + ++i;
> + }
> +
> + free(line);
> + fclose(file);
> + }
> +
> + igt_subtest("check-workaround-data-after-reset") {
> + if (IS_BROADWELL(devid))
> + check_workarounds(GPU_RESET, num_wa);
> + else
> + igt_skip_on("No Workaround table available!!\n");
> + }
> +
> + igt_subtest("check-workaround-data-after-suspend-resume") {
> + if (IS_BROADWELL(devid))
> + check_workarounds(SUSPEND_RESUME, num_wa);
> + else
> + igt_skip_on("No Workaround table available!!\n");
> + }
> +
> + free(workarounds);
> +
> + close(drm_fd);
> + igt_exit();
> +}
> --
> 2.0.4
>
>
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>
--
Paulo Zanoni
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