On Thu, Aug 14, 2014 at 02:54:25PM +0530, akash.goel@xxxxxxxxx wrote: > From: Akash Goel <akash.goel@xxxxxxxxx> > > This patch removes the check for change in pitch of frame buffer > across page flips. Since there is a support for MMIO based page > flips, we can update the plane registers to update the > FB pitch & accordingly the offsets in LINOFF/TILEOFF registers. > The plane registers are updated atomically, using the mechanism > used for Sprite planes update. Doing so also requires deferring of > MMIO flip, if issued in interrupt context. > > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx> > Signed-off-by: Pallavi G<pallavi.g@xxxxxxxxx> This looks like a separate patch from the overall work in this series. It definitely needs an i-g-t testcase, preferrably one to check that the update is indeed atomic. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++++++++++++++++++--- > drivers/gpu/drm/i915/intel_drv.h | 5 ++++ > drivers/gpu/drm/i915/intel_sprite.c | 4 +-- > 3 files changed, 54 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 47a5424..a75d1a0 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9542,6 +9542,29 @@ static bool use_mmio_flip(struct intel_engine_cs *ring, > return ring != obj->ring; > } > > +static void intel_mmio_flip_work_fn(struct work_struct *work) > +{ > + struct intel_mmio_flip *mmio_flip = > + container_of(work, struct intel_mmio_flip, work); > + struct intel_crtc *intel_crtc = > + container_of(mmio_flip, struct intel_crtc, mmio_flip); > + struct drm_device *dev = intel_crtc->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct drm_crtc *crtc = &intel_crtc->base; > + u32 start_vbl_count; > + bool atomic_update; > + > + atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); > + > + intel_mark_page_flip_active(intel_crtc); > + > + dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, > + crtc->x, crtc->y); > + > + if (atomic_update) > + intel_pipe_update_end(intel_crtc, start_vbl_count); > +} > + > static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) > { > struct drm_device *dev = intel_crtc->base.dev; > @@ -9552,6 +9575,17 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) > u32 dspcntr; > u32 reg; > > + /* if we are in interrupt context and there is a need to update > + all the plane registers (atomically), then defer the flip to > + a process context, as we can then wait for the next vblank boundary */ > + if (intel_crtc->unpin_work->update_all_plane_reg) { > + if (in_atomic()) > + schedule_work(&intel_crtc->mmio_flip.work); > + else > + intel_mmio_flip_work_fn(&intel_crtc->mmio_flip.work); > + return; > + } > + > intel_mark_page_flip_active(intel_crtc); > > reg = DSPCNTR(intel_crtc->plane); > @@ -9685,6 +9719,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > struct intel_unpin_work *work; > struct intel_engine_cs *ring; > unsigned long flags; > + bool update_all_plane_reg = 0; > int ret; > > /* > @@ -9706,7 +9741,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > if (INTEL_INFO(dev)->gen > 3 && > (fb->offsets[0] != crtc->primary->fb->offsets[0] || > fb->pitches[0] != crtc->primary->fb->pitches[0])) > - return -EINVAL; > + update_all_plane_reg = 1; > > if (i915_terminally_wedged(&dev_priv->gpu_error)) > goto out_hang; > @@ -9718,6 +9753,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > work->event = event; > work->crtc = crtc; > work->old_fb_obj = intel_fb_obj(old_fb); > + work->update_all_plane_reg = update_all_plane_reg; > INIT_WORK(&work->work, intel_unpin_work_fn); > > ret = drm_crtc_vblank_get(crtc); > @@ -9785,9 +9821,14 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > if (use_mmio_flip(ring, obj)) > ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, > page_flip_flags); > - else > - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, > - page_flip_flags); > + else { > + if (update_all_plane_reg) > + ret = -EINVAL; > + else > + ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, > + page_flip_flags); > + } > + > if (ret) > goto cleanup_unpin; > > @@ -11912,6 +11953,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > intel_crtc->cursor_cntl = ~0; > intel_crtc->cursor_size = ~0; > > + INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_fn); > + > BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || > dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); > dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index a30abd9..0cb685a 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -375,6 +375,7 @@ struct intel_pipe_wm { > struct intel_mmio_flip { > u32 seqno; > u32 ring_id; > + struct work_struct work; > }; > > struct intel_crtc { > @@ -659,6 +660,7 @@ struct intel_unpin_work { > u32 flip_count; > u32 gtt_offset; > bool enable_stall_check; > + bool update_all_plane_reg; > }; > > struct intel_set_config { > @@ -848,6 +850,9 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane); > void intel_finish_page_flip(struct drm_device *dev, int pipe); > void intel_finish_page_flip_plane(struct drm_device *dev, int plane); > > +bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count); > +void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); > + > /* shared dpll functions */ > struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); > void assert_shared_dpll(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 0bdb00b..5e4a641 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -46,7 +46,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) > return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); > } > > -static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) > +bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) > { > struct drm_device *dev = crtc->base.dev; > const struct drm_display_mode *mode = &crtc->config.adjusted_mode; > @@ -112,7 +112,7 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl > return true; > } > > -static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) > +void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) > { > struct drm_device *dev = crtc->base.dev; > enum pipe pipe = crtc->pipe; > -- > 1.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx