Re: [PATCH 1/2] drm/i915: Eliminate rmw from .update_primary_plane()

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Fri, Aug 08, 2014 at 09:51:10PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> 
> Move the entire DSPCNTR register setup into the .update_primary_plane()
> functions. That's where it belongs anyway and it'll also help 830M which
> has the extra problem that plane registers reads will return the value
> latched at the last vblank, not the value that was last written.
> 
> Also move DSPPOS and DSPSIZE setup there.
> 
> v2: Don't move variable initialization to avoid churn later
> 
> Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c | 100 +++++++++++------------------------
>  1 file changed, 32 insertions(+), 68 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 89e0ac5..4158257 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2394,12 +2394,26 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg;
> +	u32 reg = DSPCNTR(plane);
> +
> +	dspcntr = DISPPLANE_GAMMA_ENABLE;
> +
> +	if (intel_crtc->primary_enabled)
> +		dspcntr |= DISPLAY_PLANE_ENABLE;
> +
> +	if (INTEL_INFO(dev)->gen < 4) {
> +		if (intel_crtc->pipe == PIPE_B)
> +			dspcntr |= DISPPLANE_SEL_PIPE_B;
> +
> +		/* pipesrc and dspsize control the size that is scaled from,
> +		 * which should always be the user's requested size.
> +		 */
> +		I915_WRITE(DSPSIZE(plane),
> +			   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> +			   (intel_crtc->config.pipe_src_w - 1));
> +		I915_WRITE(DSPPOS(plane), 0);
> +	}
>  
> -	reg = DSPCNTR(plane);
> -	dspcntr = I915_READ(reg);
> -	/* Mask out pixel format bits in case we change it */
> -	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -2431,12 +2445,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>  		BUG();
>  	}
>  
> -	if (INTEL_INFO(dev)->gen >= 4) {
> -		if (obj->tiling_mode != I915_TILING_NONE)
> -			dspcntr |= DISPPLANE_TILED;
> -		else
> -			dspcntr &= ~DISPPLANE_TILED;
> -	}
> +	if (INTEL_INFO(dev)->gen >= 4 &&
> +	    obj->tiling_mode != I915_TILING_NONE)
> +		dspcntr |= DISPPLANE_TILED;
>  
>  	if (IS_G4X(dev))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> @@ -2480,12 +2491,16 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	unsigned long linear_offset;
>  	u32 dspcntr;
> -	u32 reg;
> +	u32 reg = DSPCNTR(plane);
> +
> +	dspcntr = DISPPLANE_GAMMA_ENABLE;
> +
> +	if (intel_crtc->primary_enabled)
> +		dspcntr |= DISPLAY_PLANE_ENABLE;
> +
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
> -	reg = DSPCNTR(plane);
> -	dspcntr = I915_READ(reg);
> -	/* Mask out pixel format bits in case we change it */
> -	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>  	switch (fb->pixel_format) {
>  	case DRM_FORMAT_C8:
>  		dspcntr |= DISPPLANE_8BPP;
> @@ -2515,12 +2530,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>  
>  	if (obj->tiling_mode != I915_TILING_NONE)
>  		dspcntr |= DISPPLANE_TILED;
> -	else
> -		dspcntr &= ~DISPPLANE_TILED;
>  
> -	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -		dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
> -	else
> +	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>  
>  	I915_WRITE(reg, dspcntr);
> @@ -3946,7 +3957,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	enum plane plane = intel_crtc->plane;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -3968,10 +3978,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
>  
>  	ironlake_set_pipeconf(crtc);
>  
> -	/* Set up the display plane register */
> -	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4059,7 +4065,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	enum plane plane = intel_crtc->plane;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4083,10 +4088,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  
>  	intel_set_pipe_csc(crtc);
>  
> -	/* Set up the display plane register */
> -	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4642,9 +4643,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	int plane = intel_crtc->plane;
>  	bool is_dsi;
> -	u32 dspcntr;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4660,27 +4659,13 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  			vlv_prepare_pll(intel_crtc);
>  	}
>  
> -	/* Set up the display plane register */
> -	dspcntr = DISPPLANE_GAMMA_ENABLE;
> -
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> -	/* pipesrc and dspsize control the size that is scaled from,
> -	 * which should always be the user's requested size.
> -	 */
> -	I915_WRITE(DSPSIZE(plane),
> -		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> -		   (intel_crtc->config.pipe_src_w - 1));
> -	I915_WRITE(DSPPOS(plane), 0);
> -
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	I915_WRITE(DSPCNTR(plane), dspcntr);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> @@ -4735,8 +4720,6 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe;
> -	int plane = intel_crtc->plane;
> -	u32 dspcntr;
>  
>  	WARN_ON(!crtc->enabled);
>  
> @@ -4745,32 +4728,13 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  
>  	i9xx_set_pll_dividers(intel_crtc);
>  
> -	/* Set up the display plane register */
> -	dspcntr = DISPPLANE_GAMMA_ENABLE;
> -
> -	if (pipe == 0)
> -		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
> -	else
> -		dspcntr |= DISPPLANE_SEL_PIPE_B;
> -
>  	if (intel_crtc->config.has_dp_encoder)
>  		intel_dp_set_m_n(intel_crtc);
>  
>  	intel_set_pipe_timings(intel_crtc);
>  
> -	/* pipesrc and dspsize control the size that is scaled from,
> -	 * which should always be the user's requested size.
> -	 */
> -	I915_WRITE(DSPSIZE(plane),
> -		   ((intel_crtc->config.pipe_src_h - 1) << 16) |
> -		   (intel_crtc->config.pipe_src_w - 1));
> -	I915_WRITE(DSPPOS(plane), 0);
> -
>  	i9xx_set_pipeconf(intel_crtc);
>  
> -	I915_WRITE(DSPCNTR(plane), dspcntr);
> -	POSTING_READ(DSPCNTR(plane));
> -
>  	dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>  					       crtc->x, crtc->y);
>  
> -- 
> 1.8.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx





[Index of Archives]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]
  Powered by Linux