From: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx> Currently in BDW workarounds are initialized in init_clock_gating() but some of them are lost followed by a gpu reset. The solution is to apply them in golden render state which keeps them valid when starting with an uninitialized state. First patch adds workaround registers to golden render state. This patch uses functions which are part two other patches, one of which is not yet sent for upstream [2]. [1] https://www.mail-archive.com/intel-gfx@xxxxxxxxxxxxxxxxxxxxx/msg43044.html [2] From cc8f2f657c44d7c017e70e1af11b4513358b6a0a Mon Sep 17 00:00:00 2001 From: Deepak S <deepak.s@xxxxxxxxxxxxxxx> Date: Sat, 2 Aug 2014 20:05:07 +0530 Subject: [PATCH 2/3] tools/null_state_render: Add ROW CHICKEN BIT Registers to golden render state As per, latest Bspec, some of the RenderCS registers are expected to be added in context. We achive this by adding the registers Golden render state. Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx> Second patch adds a simple test which captures workaround register data before and after a gpu reset and compares them. Suspend/Resume is currently not working hence it is not tested. The test uses intel_reg_read() to read register data but I observed that this value is different from the one compared to using I915_READ() from within the driver. e.g., in case of CACHE_MODE_1 with WA applied it should be 0x01C0. intel_reg_read() gives 0x0180 whereas with I915_READ() it is 0x01C0. Arun Siluvery (2): tools/null_state_render: Add BDW workarounds to golden render state igt/gem_workarounds: igt to test workaround registers lib/intel_reg.h | 30 ++++ tests/Makefile.sources | 1 + tests/gem_workarounds.c | 211 ++++++++++++++++++++++++++ tools/null_state_gen/intel_renderstate_gen8.c | 37 +++++ 4 files changed, 279 insertions(+) create mode 100644 tests/gem_workarounds.c -- 2.0.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
