On Thu, Aug 07, 2014 at 04:29:53PM +0200, Jiri Kosina wrote: > Withtout this, ring initialization fails reliabily during resume with > > [drm:init_ring_common] *ERROR* render ring initialization failed ctl 0001f001 head ffffff8804 tail 00000000 start 000e4000 > > This is not a complete fix, but it is verified to make the ring > initialization failures during resume much less likely. > > We were not able to root-cause this bug (likely HW-specific to Gen4 chips) > yet. This is therefore used as a ducttape before problem is fully > understood and proper fix created, so that people don't suffer from > completely unusable systems in the meantime. > > The discussion and debugging is happening at > > https://bugs.freedesktop.org/show_bug.cgi?id=76554 > > Signed-off-by: Jiri Kosina <jkosina@xxxxxxx> Ok, picked this one here, has the nicer commit message ;-) -Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 279488a..7add7ee 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -517,6 +517,9 @@ static int init_ring_common(struct intel_engine_cs *ring) > else > ring_setup_phys_status_page(ring); > > + /* Enforce ordering by reading HEAD register back */ > + I915_READ_HEAD(ring); > + > /* Initialize the ring. This must happen _after_ we've cleared the ring > * registers with the above sequence (the readback of the HEAD registers > * also enforces ordering), otherwise the hw might lose the new ring > -- > Jiri Kosina > SUSE Labs -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
