On Wed, Jul 30, 2014 at 11:01:48PM -0700, Keith Packard wrote: > Eric Anholt <eric@xxxxxxxxxx> writes: > > > Keith Packard <keithp@xxxxxxxxxx> writes: > > > >> Make sure the pitch and tiling are correct. > >> Make sure there's a BO we can get at. > > > > I thought we couldn't change these parameters, but now I can't find what > > prevents them from changing. Can you cite sources? > > Looks like we *can* change tiling format. That actually makes me kinda > happy as that explains why we were able to allocate a linear frame > buffer for the X front buffer (due to a bug) and page flip to DRI3 > buffers which are always tiled. > > However, we can't change the pitch. From the kernel driver: > > /* > * TILEOFF/LINOFF registers can't be changed via MI display flips. > * Note that pitch changes could also affect these register. > */ > if (INTEL_INFO(dev)->gen > 3 && > (fb->offsets[0] != crtc->primary->fb->offsets[0] || > fb->pitches[0] != crtc->primary->fb->pitches[0])) > return -EINVAL; > > I'll remove the tiling check. Now that we have mmio flips in the kernel we can start to relax that restriction. That still needs a bit more work in the mmio flip code but I believe some people working on just that. We could even change the pixel format, except a check was added to drm_mode_page_flip_ioctl() to prevent that, so I guess it was deemed that the API isn't meant to allow that. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
