On Wed, Jul 30, 2014 at 05:43:10PM -0300, Paulo Zanoni wrote: > 2014-06-27 20:04 GMT-03:00 <ville.syrjala@xxxxxxxxxxxxxxx>: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > The VLV/CHV DDL registers are uniform, and neatly enough the register > > offsets are sane so we can easily unify them to a single set of defines > > and just pass the pipe as the parameter to compute the register offset. > > What the commit message doesn't tell is that now we will call > vlv_compute_drain_latency() for pipe C on CHV since I see CHV is > defined with num_pipes=3. I think this is quite an important detail, > since it's the only way this patch changes the behavior of the code. > > If that is intentional and correct, then I suggest amending the commit > message, even maybe the patch title. Then you can add: Reviewed-by: > Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>. One of the following patches will add a proper cherryview_update_wm() function which also fills out the actual watermarks for pipe C. Ideally I probably should have reordered these patches. But I'll add a note of some sort here to avoid bigger reordering pains now. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
