On Wed, Jul 30, 2014 at 09:26:17AM -0700, Rodrigo Vivi wrote:
> With this bit enabled, HW changes the color when compressing frames for
> debug purposes.
>
> ALthough the simple way to enable a single bit is over intel_reg_write,
> this value is overwriten on next update_fbc so depending on the workload
> it is not possible to set this bit with intel-gpu-tools. So this patch
> introduces a persistent way to enable false color over debugfs.
>
> v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
> v3: (Ville) only do false color for IVB+ since according to spec bit is
> MBZ before IVB.
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Ben Widawsky <ben@xxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
I don't quite understand the motivation for a get() other than debugging
the interface itself (if your set is broken). If anything, get should
read back the register in case you're trying to debug funky colors, but
I am not strongly opinionated here.
Just to make sure, false color works on VLV/CHV (for the gen check)?
With the above address:
Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> 4 files changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9e737b7..bcfdc00 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1433,6 +1433,47 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
> return 0;
> }
>
> +static int i915_fbc_fc_get(void *data, u64 *val)
> +{
> + struct drm_device *dev = data;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (INTEL_INFO(dev)->gen < 7)
> + return -ENODEV;
> +
> + drm_modeset_lock_all(dev);
> + *val = dev_priv->fbc.false_color;
> + drm_modeset_unlock_all(dev);
> +
> + return 0;
> +}
> +
> +static int i915_fbc_fc_set(void *data, u64 val)
> +{
> + struct drm_device *dev = data;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 reg;
> +
> + if (INTEL_INFO(dev)->gen < 7)
> + return -ENODEV;
> +
> + drm_modeset_lock_all(dev);
> +
> + reg = I915_READ(ILK_DPFC_CONTROL);
> + dev_priv->fbc.false_color = val;
> +
> + I915_WRITE(ILK_DPFC_CONTROL, val ?
> + (reg | FBC_CTL_FALSE_COLOR) :
> + (reg & ~FBC_CTL_FALSE_COLOR));
> +
> + drm_modeset_unlock_all(dev);
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
> + i915_fbc_fc_get, i915_fbc_fc_set,
> + "%llu\n");
> +
> static int i915_ips_status(struct seq_file *m, void *unused)
> {
> struct drm_info_node *node = m->private;
> @@ -3957,6 +3998,7 @@ static const struct i915_debugfs_files {
> {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
> {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
> {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
> + {"i915_fbc_false_color", &i915_fbc_fc_fops},
> };
>
> void intel_display_crc_init(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18c9ad8..3018bf5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -636,6 +636,8 @@ struct i915_fbc {
> struct drm_mm_node compressed_fb;
> struct drm_mm_node *compressed_llb;
>
> + bool false_color;
> +
> struct intel_fbc_work {
> struct delayed_work work;
> struct drm_crtc *crtc;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 28e21ed..b5d295a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1540,6 +1540,7 @@ enum punit_power_well {
> /* Framebuffer compression for Ironlake */
> #define ILK_DPFC_CB_BASE 0x43200
> #define ILK_DPFC_CONTROL 0x43208
> +#define FBC_CTL_FALSE_COLOR (1<<10)
> /* The bit 28-8 is reserved */
> #define DPFC_RESERVED (0x1FFFFF00)
> #define ILK_DPFC_RECOMP_CTL 0x4320c
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1ddd4df..338a80b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -309,6 +309,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
>
> dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
>
> + if (dev_priv->fbc.false_color)
> + dpfc_ctl |= FBC_CTL_FALSE_COLOR;
> +
> I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>
> if (IS_IVYBRIDGE(dev)) {
> --
> 1.9.3
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
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