On Wed, Jul 30, 2014 at 03:57:32PM +0300, Imre Deak wrote: > Just like during booting the BIOS can leave the VDD bit enabled after > system resume. So apply the same state sanitization there too. This > fixes a problem where after resume the port power domain refcount gets > unbalanced. > > Reported-and-tested-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1edfd1a..fdb5657 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -12977,6 +12977,12 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, > /* HW state is read out, now we need to sanitize this mess. */ > list_for_each_entry(encoder, &dev->mode_config.encoder_list, > base.head) { > + /* > + * Do the following only during resume, since at driver > + * loading it's done early when initializing the encoder. > + */ > + if (force_restore) > + intel_edp_panel_vdd_sanitize(encoder); This should be put into an encoder->reset callback. -Daniel > intel_sanitize_encoder(encoder); > } > > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx