On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Both VLV and CHV handle the cmnreset stuff in the power well code now,
> so intel_reset_dpio() is no longer needed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 -------------------------------
> 1 file changed, 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a16f635..3cd73f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1511,34 +1511,6 @@ static void intel_init_dpio(struct drm_device *dev)
> }
> }
>
> -static void intel_reset_dpio(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (IS_CHERRYVIEW(dev)) {
> - enum dpio_phy phy;
> - u32 val;
> -
> - for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
> - /* Poll for phypwrgood signal */
> - if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
> - PHY_POWERGOOD(phy), 1))
> - DRM_ERROR("Display PHY %d is not power up\n", phy);
> -
> - /*
> - * Deassert common lane reset for PHY.
> - *
> - * This should only be done on init and resume from S3
> - * with both PLLs disabled, or we risk losing DPIO and
> - * PLL synchronization.
> - */
> - val = I915_READ(DISPLAY_PHY_CONTROL);
> - I915_WRITE(DISPLAY_PHY_CONTROL,
> - PHY_COM_LANE_RESET_DEASSERT(phy, val));
> - }
> - }
> -}
> -
> static void vlv_enable_pll(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -12473,8 +12445,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
>
> intel_init_clock_gating(dev);
>
> - intel_reset_dpio(dev);
> -
> intel_enable_gt_powersave(dev);
> }
>
> @@ -12545,7 +12515,6 @@ void intel_modeset_init(struct drm_device *dev)
> }
>
> intel_init_dpio(dev);
> - intel_reset_dpio(dev);
>
> intel_cpu_pll_init(dev);
> intel_shared_dpll_init(dev);
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