On 23 July 2014 15:11, Daniel Vetter <daniel@xxxxxxxx> wrote: > On Sat, Jul 12, 2014 at 10:02:27AM +0530, sagar.a.kamble@xxxxxxxxx wrote: >> From: Borun Fu <borun.fu@xxxxxxxxx> >> >> On VLV, after i915_pm_suspend display power wells are staying >> power ungated. So, after initiating mem sleep "echo mem > /sys/power/state" >> Display is staing D0 State. There might be better way/place to power gate >> these wells. Also, we need to make sure that if wells are power gated due to >> DPMS OFF sequence, they need not be turned off by i915_pm_suspend again. >> >> v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells. >> [Daniel] >> >> Cc: Imre Deak <imre.deak@xxxxxxxxx> >> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx> >> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> >> Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848 > > s-o-b from the original author (Borun Fu) missing. Added myself since we > all work for the same company, but please don't forget this. Every person > including the original author, who handles a patch must add their sob > line. > -Daniel Is this queued or on its way, I was getting a warning on HSW about not entering pc8+ due to display with MST enabled, and I thought it was MSTs fault, but I suspect its just this, mode set turns the global resources power well on, but nothing ever turns it off. Dave. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
