From: Thomas Daniel <thomas.daniel@xxxxxxxxx> For a description of this patchset, please check the previous cover letters: [1], [2], [3] and [4]. I have taken ownership of this patchset from Oscar, and this version represents his last work on the execlists patchset. The narrative below is from him. I have been given some grace period to fix the remaining issues in Execlists before I move to a different project, and this is the result. There are very little differences between this v5 and the v4 I sent out last week, so I was unsure whether to drop a new patchbomb or simply reply to the patches that have changed, but I decided for the former to make the review easier. The changes are: - New prep-work patch to prevent a potential problem with the legacy ringbuffer submission extraction that was done earlier. - Do the remaining intel_runtime_put while purging the execlists queue during reset. - Check arguments before doing stuff in intel_execlists_submission. Also, get rel_constants parsing right. - Do gen8_emit_flush = gen6_ring_flush + gen6_bsd_ring_flush. - New patches for pinning context and ringbuffer backing objects on-demand (before I was pinning on interrupt time, which was a no-no). These fix the reamining eviction issues I was seeing. The previous comment about the WAs still applies. I reproduce it here for completeness: "One other caveat I have noticed is that many WAs in gen8_init_clock_gating (those that affect registers that now exist per-context) can get lost in the render default context. The reason is, in Execlists, a context is saved as soon as head = tail (with MI_SET_CONTEXT, however, the context wouldn't be saved until you tried to restore a different context). As we are sending the golden state batchbuffer to the render ring as soon as the rings are initialized, we are effectively saving the default context before gen8_init_clock_gating has an opportunity to set the WAs. I haven't noticed any ill-effect from this (yet) but it would be a good idea to move the WAs somewhere else (ring init looks like a good place). I believe there is already work in progress to create a new WA architecture, so this can be tackled there." The previous IGT test [4] still applies. There are three pending issues: - The test gem_close_race warns about "scheduling while atomic" when the shrinker gets called. Without Execlists, the shrinker does not get called at all (which kind of makes sense) but the tests timeouts before finishing. - The test gem_concurrent_blit fails in the gtt-* subtests: some pixels (14, to be exact) do not get copied correctly from one bo to another. Funnily enough, the tests pass if I do a i915 module reload first (./tests/drv_module_reload). Yesterday I dumped all the registers in the chip before and after a module reload (attached), but I havenŽt found any meaningful difference yet. - When I try to run a whole IGT suite using Piglit, sometimes I hit the BUG_ON(!i915_gem_obj_is_pinned(ctx_obj0)) in execlists_submit_context(). I havenŽt managed to reproduce the problem at will, but there is obviously something wrong with the last two Execlists patches. Keep the r-b tags coming, please!! -- Oscar [1] http://lists.freedesktop.org/archives/intel-gfx/2014-March/042563.html [2] http://lists.freedesktop.org/archives/intel-gfx/2014-May/044847.html [3] http://lists.freedesktop.org/archives/intel-gfx/2014-June/047138.html [4] http://lists.freedesktop.org/archives/intel-gfx/2014-July/048944.html [5] http://lists.freedesktop.org/archives/intel-gfx/2014-May/044846.html Ben Widawsky (2): drm/i915/bdw: Implement context switching (somewhat) drm/i915/bdw: Print context state in debugfs Michel Thierry (1): drm/i915/bdw: Two-stage execlist submit process Oscar Mateo (39): drm/i915: Reorder the actual workload submission so that args checking is done earlier drm/i915/bdw: New source and header file for LRs, LRCs and Execlists drm/i915/bdw: Macro for LRCs and module option for Execlists drm/i915/bdw: Initialization for Logical Ring Contexts drm/i915/bdw: Introduce one context backing object per engine drm/i915/bdw: A bit more advanced LR context alloc/free drm/i915/bdw: Allocate ringbuffers for Logical Ring Contexts drm/i915/bdw: Add a context and an engine pointers to the ringbuffer drm/i915/bdw: Populate LR contexts (somewhat) drm/i915/bdw: Deferred creation of user-created LRCs drm/i915/bdw: Render moot context reset and switch with Execlists drm/i915/bdw: Don't write PDP in the legacy way when using LRCs drm/i915: Abstract the legacy workload submission mechanism away drm/i915/bdw: Skeleton for the new logical rings submission path drm/i915/bdw: Generic logical ring init and cleanup drm/i915/bdw: GEN-specific logical ring init drm/i915/bdw: GEN-specific logical ring set/get seqno drm/i915/bdw: New logical ring submission mechanism drm/i915/bdw: GEN-specific logical ring emit request drm/i915/bdw: GEN-specific logical ring emit flush drm/i915/bdw: Emission of requests with logical rings drm/i915/bdw: Ring idle and stop with logical rings drm/i915/bdw: Interrupts with logical rings drm/i915/bdw: GEN-specific logical ring emit batchbuffer start drm/i915/bdw: Workload submission mechanism for Execlists drm/i915/bdw: Always use MMIO flips with Execlists drm/i915/bdw: Render state init for Execlists drm/i915/bdw: Write the tail pointer, LRC style drm/i915/bdw: Avoid non-lite-restore preemptions drm/i915/bdw: Help out the ctx switch interrupt handler drm/i915/bdw: Make sure gpu reset still works with Execlists drm/i915/bdw: Make sure error capture keeps working with Execlists drm/i915/bdw: Disable semaphores for Execlists drm/i915/bdw: Display execlists info in debugfs drm/i915/bdw: Display context backing obj & ringbuffer info in debugfs drm/i915/bdw: Document Logical Rings, LR contexts and Execlists drm/i915/bdw: Enable Logical Ring Contexts (hence, Execlists) drm/i915/bdw: Pin the context backing objects to GGTT on-demand drm/i915/bdw: Pin the ringbuffer backing object to GGTT on-demand Thomas Daniel (1): drm/i915/bdw: Handle context switch events Documentation/DocBook/drm.tmpl | 5 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 157 ++- drivers/gpu/drm/i915/i915_drv.c | 4 + drivers/gpu/drm/i915/i915_drv.h | 47 +- drivers/gpu/drm/i915/i915_gem.c | 132 +- drivers/gpu/drm/i915/i915_gem_context.c | 56 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 118 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 + drivers/gpu/drm/i915/i915_gem_render_state.c | 40 +- drivers/gpu/drm/i915/i915_gem_render_state.h | 47 + drivers/gpu/drm/i915/i915_gpu_error.c | 22 +- drivers/gpu/drm/i915/i915_irq.c | 44 +- drivers/gpu/drm/i915/i915_params.c | 6 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_display.c | 2 + drivers/gpu/drm/i915/intel_lrc.c | 1802 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.h | 115 ++ drivers/gpu/drm/i915/intel_renderstate.h | 8 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 166 ++- drivers/gpu/drm/i915/intel_ringbuffer.h | 41 +- 21 files changed, 2622 insertions(+), 201 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_gem_render_state.h create mode 100644 drivers/gpu/drm/i915/intel_lrc.c create mode 100644 drivers/gpu/drm/i915/intel_lrc.h -- 1.9.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
