On Mon, Jul 14, 2014 at 12:10:45PM -0700, Todd Previte wrote:
> Implements basic link training functionality for Displayport automated compliance
> testing.
>
> Signed-off-by: Todd Previte <tprevite@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 47 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 65830e9..e4b31ad 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3427,6 +3427,53 @@ static uint8_t
> intel_dp_autotest_link_training(struct intel_dp *intel_dp)
> {
> uint8_t test_result = DP_TEST_NAK;
> + uint8_t rxdata[2];
> + uint8_t link_status[DP_LINK_STATUS_SIZE];
> + int bytes_ret = 0;
> + struct drm_connector *connector = &intel_dp->attached_connector->base;
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(&intel_dp->attached_connector->encoder->base);
> +
> + /* Read test parameters */
> + bytes_ret = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_LINK_RATE, rxdata, 2);
> +
> + /* Set link rate directly */
> + intel_dp->link_bw = rxdata[0];
> + /* Preserve 7:5 when setting lane count */
> + intel_dp->lane_count &= 0xE0;
> + intel_dp->lane_count |= rxdata[1];
This won't work - if you change the link config you need to do a full
recomputation of the modeset config and a full modeset. No, we dont (yet)
have the infrastructure for this, which is why dp is such a pain since we
can change the link config once we've decided on something :(
-Daniel
> +
> + DRM_DEBUG_KMS("Displayport: Link training testing - %d lanes @ %02x link rate\n",
> + intel_dp->lane_count, intel_dp->link_bw);
> +
> + /* Train the link */
> + intel_dp->DP = intel_dig_port->saved_port_bits |
> + DDI_BUF_CTL_ENABLE |
> + DDI_BUF_EMP_400MV_0DB_HSW;
> + intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
> +
> + if (!intel_dp_start_link_train(intel_dp)) {
> + DRM_DEBUG_KMS("Displayport: intel_dp_start_link_train() failed\n");
> + test_result = false;
> + }
> + if (!intel_dp_complete_link_train(intel_dp)) {
> + DRM_DEBUG_KMS("Displayport: intel_dp_complete_link_train() failed\n");
> + test_result = false;
> + }
> + if (!intel_dp_stop_link_train(intel_dp)) {
> + DRM_DEBUG_KMS("Displayport: intel_dp_stop_link_train() failed\n");
> + test_result = false;
> + }
> +
> + /* Check link status for successful completion */
> + if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))
> + test_result = true;
> +
> + if (test_result == false) {
> + /* Clear link training here */
> + intel_dp_set_idle_link_train(intel_dp);
> + }
> +
> return test_result;
> }
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
