L3SQCREG4 LQSC RO PERF DIS must be programmed by software to 1h
(Disable) to work around a Gsync Issue in HDC.
Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f0c759..9058ae4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4714,6 +4714,7 @@ enum punit_power_well {
#define GEN8_TAG_CLK_OFFTIME_MASK (~((1<<23) | (1<<22) | (1<<21) | (1<<20)))
#define GEN8_L3SQCREG4 0xb118
+#define GEN8_L3SQCREG4_LQSC_RO_PERF_DISABLE (1<<27)
#define GEN8_PIPELINE_FLUSH_COHERENT_LINES (1<<21)
/* WaCatErrorRejectionIssue */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c16dcb3..41a438e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5495,8 +5495,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) &
~GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE);
+ /* WaDisableLSQCROPERFforOCL:bdw */
/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN8_L3SQCREG4_LQSC_RO_PERF_DISABLE |
GEN8_PIPELINE_FLUSH_COHERENT_LINES);
/*
--
1.9.0
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